X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=spike_main%2Fspike.cc;h=eb57baf5abfe7360ebcd4010dde0807eda8df032;hb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e;hp=3061b106ff9a34318b25f4bd7db04b9868ead390;hpb=85efaaaba8938a7026d5d9203c09e8be0fd66130;p=riscv-isa-sim.git

diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index 3061b10..eb57baf 100644
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -25,16 +25,21 @@ static void help()
   fprintf(stderr, "  -g                    Track histogram of PCs\n");
   fprintf(stderr, "  -l                    Generate a log of execution\n");
   fprintf(stderr, "  -h                    Print this help message\n");
-  fprintf(stderr, "  -H                 Start halted, allowing a debugger to connect\n");
+  fprintf(stderr, "  -H                    Start halted, allowing a debugger to connect\n");
   fprintf(stderr, "  --isa=<name>          RISC-V ISA string [default %s]\n", DEFAULT_ISA);
   fprintf(stderr, "  --pc=<address>        Override ELF entry point\n");
+  fprintf(stderr, "  --hartids=<a,b,...>   Explicitly specify hartids, default is 0,1,...\n");
   fprintf(stderr, "  --ic=<S>:<W>:<B>      Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>        W ways, and B-byte blocks (with S and\n");
   fprintf(stderr, "  --l2=<S>:<W>:<B>        B both powers of 2).\n");
   fprintf(stderr, "  --extension=<name>    Specify RoCC Extension\n");
   fprintf(stderr, "  --extlib=<name>       Shared library to load\n");
   fprintf(stderr, "  --rbb-port=<port>     Listen on <port> for remote bitbang connection\n");
-  fprintf(stderr, "  --dump-dts  Print device tree string and exit\n");
+  fprintf(stderr, "  --dump-dts            Print device tree string and exit\n");
+  fprintf(stderr, "  --progsize=<words>    Progsize for the debug module [default 2]\n");
+  fprintf(stderr, "  --debug-sba=<bits>    Debug bus master supports up to "
+      "<bits> wide accesses [default 0]\n");
+  fprintf(stderr, "  --debug-auth          Debug module requires debugger to authenticate\n");
   exit(1);
 }
 
@@ -45,6 +50,8 @@ static std::vector<std::pair<reg_t, mem_t*>> make_mems(const char* arg)
   auto mb = strtoull(arg, &p, 0);
   if (*p == 0) {
     reg_t size = reg_t(mb) << 20;
+    if (size != (size_t)size)
+      throw std::runtime_error("Size would overflow size_t");
     return std::vector<std::pair<reg_t, mem_t*>>(1, std::make_pair(reg_t(DRAM_BASE), new mem_t(size)));
   }
 
@@ -84,6 +91,9 @@ int main(int argc, char** argv)
   const char* isa = DEFAULT_ISA;
   uint16_t rbb_port = 0;
   bool use_rbb = false;
+  unsigned progsize = 2;
+  unsigned max_bus_master_bits = 0;
+  bool require_authentication = false;
   std::vector<int> hartids;
 
   auto const hartids_parser = [&](const char *s) {
@@ -124,13 +134,19 @@ int main(int argc, char** argv)
       exit(-1);
     }
   });
+  parser.option(0, "progsize", 1, [&](const char* s){progsize = atoi(s);});
+  parser.option(0, "debug-sba", 1,
+      [&](const char* s){max_bus_master_bits = atoi(s);});
+  parser.option(0, "debug-auth", 0,
+      [&](const char* s){require_authentication = true;});
 
   auto argv1 = parser.parse(argv);
   std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
   if (mems.empty())
     mems = make_mems("2048");
 
-  sim_t s(isa, nprocs, halted, start_pc, mems, htif_args, std::move(hartids));
+  sim_t s(isa, nprocs, halted, start_pc, mems, htif_args, std::move(hartids),
+      progsize, max_bus_master_bits, require_authentication);
   std::unique_ptr<remote_bitbang_t> remote_bitbang((remote_bitbang_t *) NULL);
   std::unique_ptr<jtag_dtm_t> jtag_dtm(new jtag_dtm_t(&s.debug_module));
   if (use_rbb) {