X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fbsv_lib%2Fsoc_template.bsv;h=cd2fcefb7066beb3d48502d4d09aba337fbe83d9;hb=aeac06c9f7dd07b3fbe7c236c5eefd76c7782ab6;hp=56978c647adb66dcc33864a5688384d3390051e5;hpb=00a8b07dc55f3db59fda9f526a4a18c1b5c09c63;p=pinmux.git diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv index 56978c6..cd2fcef 100644 --- a/src/bsv/bsv_lib/soc_template.bsv +++ b/src/bsv/bsv_lib/soc_template.bsv @@ -28,7 +28,7 @@ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------- */ -package Soc; +package socgen; /*====== Package imports === */ import FIFO::*; import FIFOF::*; @@ -38,92 +38,84 @@ package Soc; import Vector::*; import Connectable::*; import Clocks::*; - /*========================== */ + /*=== Project imports === */ + import ifc_sync:: *; import ConcatReg::*; import AXI4_Types::*; import AXI4_Fabric::*; import defined_types::*; import MemoryMap :: *; import slow_peripherals::*; + import fast_memory_map::*; + import slow_memory_map::*; +`ifdef DEBUG `include "defines.bsv" +`endif `include "instance_defines.bsv" + `include "core_parameters.bsv" {8} - /*====== AXI4 slave declarations =======*/ -{3} - /*====== AXI4 Master declarations =======*/ -{4} - - `ifdef DMA - import DMA :: *; - `endif - `ifdef BOOTROM - import BootRom ::*; - `endif - `ifdef SDRAM - import sdr_top :: *; + `ifdef DMA + import DMA :: *; + `endif + `ifdef BOOTROM + import BootRom ::*; + `endif + `ifdef BRAM + import Memory_AXI4 ::*; + `endif + `ifdef TCMemory + import TCM::*; + `endif + `ifdef Debug + import DebugModule::*; + `else + import core::*; + `endif + `ifdef VME + import vme_top ::*; `endif - `ifdef BRAM - import Memory_AXI4 ::*; - `endif - `ifdef TCMemory - import TCM::*; - `endif - `ifdef Debug - import jtagdtm::*; - import DebugModule::*; - `else - import core::*; - `endif -`ifdef VME - import vme_top ::*; -`endif -`ifdef VME - import vme_master::*; -`endif -`ifdef FlexBus - import FlexBus_Types::*; -`endif + `ifdef VME + import vme_master::*; + `endif {0} /*========================= */ interface Ifc_Soc; - interface SP_ios slow_ios; + interface SP_dedicated_ios slow_ios; + interface IOCellSide iocell_side; (*always_ready,always_enabled*) method Action boot_sequence(Bit#(1) bootseq); - - `ifdef SDRAM - (*always_ready*) interface Ifc_sdram_out sdram_out; + + `ifdef DDR + (*prefix="M_AXI"*) interface + AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master; `endif - `ifdef DDR - (*prefix="M_AXI"*) interface - AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master; - `endif `ifdef HYPER - (*always_ready,always_enabled*) - interface Ifc_flash ifc_flash; - `endif - /*=============================================== */ - `ifdef VME - interface Vme_out proc_ifc; - interface Data_bus_inf proc_dbus; + (*always_ready,always_enabled*) + interface Ifc_flash ifc_flash; `endif - `ifdef FlexBus - interface FlexBus_Master_IFC flexbus_out; + /*=============================================== */ + `ifdef VME + interface Vme_out proc_ifc; + interface Data_bus_inf proc_dbus; `endif {1} endinterface + + //============ mkSoc module ================= + (*synthesize*) module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock, - Reset uart_reset, Clock clk0, Clock tck, Reset trst + Reset uart_reset, Clock clk0, Reset rst0, Clock tck, Reset trst `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc); Clock core_clock <-exposeCurrentClock; // slow peripheral clock Reset core_reset <-exposeCurrentReset; // slow peripheral reset {2} - `ifdef Debug + `ifdef Debug Ifc_DebugModule core<-mkDebugModule(reset_vector); `else Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector); @@ -131,10 +123,7 @@ package Soc; `ifdef BOOTROM BootRom_IFC bootrom <-mkBootRom; `endif - `ifdef SDRAM - Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0); - `endif - `ifdef BRAM + `ifdef BRAM Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <- mkMemory("code.mem.MSB","code.mem.LSB","MainMEM"); `endif @@ -147,23 +136,24 @@ package Soc; `ifdef VME Ifc_vme_top vme <-mkvme_top(); `endif - `ifdef FlexBus - AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0) - flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor; - `endif Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals( - core_clock, core_reset, uart_clock, - uart_reset, clocked_by slow_clock , reset_by slow_reset - `ifdef PWM_AXI4Lite , ext_pwm_clock `endif ); + core_clock, core_reset, + uart_clock, uart_reset, + clocked_by slow_clock, reset_by slow_reset + `ifdef PWM_AXI4Lite , ext_pwm_clock `endif ); + + // clock sync mkConnections +{12} - // Fabric - AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE) - fabric <- mkAXI4_Fabric(fn_addr_to_slave_num); + // Fabric + AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves, + `PADDR, `DATA,`USERSPACE) + fabric <- mkAXI4_Fabric(fn_addr_to_slave_num); - // Connect traffic generators to fabric - mkConnection (core.dmem_master,fabric.v_from_masters + // Connect traffic generators to fabric + mkConnection (core.dmem_master,fabric.v_from_masters [fromInteger(valueOf(Dmem_master_num))]); - mkConnection (core.imem_master, fabric.v_from_masters + mkConnection (core.imem_master, fabric.v_from_masters [fromInteger(valueOf(Imem_master_num))]); `ifdef Debug mkConnection (core.debug_master, fabric.v_from_masters @@ -173,6 +163,7 @@ package Soc; mkConnection (dma.mmu, fabric.v_from_masters [fromInteger(valueOf(DMA_master_num))]); `endif +{13} // Connect fabric to memory slaves @@ -181,14 +172,6 @@ package Soc; [fromInteger(valueOf(Debug_slave_num))], core.debug_slave); `endif - `ifdef SDRAM - mkConnection (fabric.v_to_slaves - [fromInteger(valueOf(Sdram_slave_num))], - sdram.axi4_slave_sdram); // - mkConnection (fabric.v_to_slaves - [fromInteger(valueOf(Sdram_cfg_slave_num))], - sdram.axi4_slave_cntrl_reg); // - `endif `ifdef BRAM mkConnection(fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))], @@ -217,13 +200,11 @@ package Soc; [fromInteger(valueOf(VME_slave_num))], vme.slave_axi_vme); `endif - `ifdef FlexBus - mkConnection (fabric.v_to_slaves - [fromInteger(valueOf(FlexBus_slave_num))], - flexbus.axi_side); - `endif -// fabric connections +// pin connections +{9} + + // fabric connections {5} `ifdef DMA @@ -275,7 +256,7 @@ package Soc; mkSyncBitToCC(slow_clock,slow_reset); SyncBitIfc#(Bit#(1)) clint_msip_int <- mkSyncBitToCC(slow_clock,slow_reset); - Reg#(Bit#(`Reg_width)) clint_mtime_value <- + Reg#(Bit#(`DATA)) clint_mtime_value <- mkSyncRegToCC(0,slow_clock,slow_reset); rule synchronize_clint_data; clint_mtip_int.send(slow_peripherals.mtip_int); @@ -304,20 +285,16 @@ package Soc; `ifdef VME interface proc_ifc = vme.proc_ifc; interface proc_dbus = vme.proc_dbus; - `endif - `ifdef FlexBus - interface flexbus_out = flexbus.flexbus_side; `endif method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq); - `ifdef SDRAM - interface sdram_out=sdram.ifc_sdram_out; - `endif `ifdef DDR interface master=fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))]; `endif - interface slow_ios=slow_peripherals.slow_ios; + interface slow_ios = slow_peripherals.slow_ios; + interface iocell_side = slow_peripherals.iocell_side; + {6} endmodule endpackage