X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Finterface_decl.py;h=83ba313e350522cf4bba37df2227cfe2755fc905;hb=92cd44bcd9a90ea2f1eb0f49c9a498fde092f331;hp=78e774cff13ab649b8828cb222da845de10c800b;hpb=272836c4fabf7a7ab23fe58349e01c9471e85d5a;p=pinmux.git diff --git a/src/bsv/interface_decl.py b/src/bsv/interface_decl.py index 78e774c..83ba313 100644 --- a/src/bsv/interface_decl.py +++ b/src/bsv/interface_decl.py @@ -242,7 +242,6 @@ class InterfaceFmt(object): return '\n' + res + '\n' - class Interface(PeripheralIface, InterfaceFmt): """ create an interface from a list of pinspecs. each pinspec is a dictionary, see Pin class arguments @@ -443,7 +442,7 @@ class InterfaceBus(InterfaceFmt): self.buspins = filter(lambda x: x.name_.startswith(self.fbus), self.pins_) self.nonbuspins = filter(lambda x: not x.name_.startswith(self.fbus), - self.pins_) + self.pins_) def get_nonbuspins(self): return self.nonbuspins @@ -538,23 +537,43 @@ class InterfaceLCD(InterfaceBus, Interface): InterfaceBus.__init__(self, self.pins, False, ['data_out', None, None], "Bit#({0})", "out") + +class InterfaceSDRAM(InterfaceMultiBus, Interface): + + def __init__(self, ifacename, pinspecs, ganged=None, single=False): + Interface.__init__(self, ifacename, pinspecs, ganged, single) + InterfaceMultiBus.__init__(self, self.pins) + self.add_bus(False, ['dqm', None, None], + "Bit#({0})", "sdrdqm") + self.add_bus(True, ['d_out', 'd_out_en', 'd_in'], + "Bit#({0})", "sdrd") + self.add_bus(False, ['ad', None, None], + "Bit#({0})", "sdrad") + self.add_bus(False, ['ba', None, None], + "Bit#({0})", "sdrba") + + def ifacedef2(self, *args): + return InterfaceMultiBus.ifacedef2(self, *args) + + class InterfaceFlexBus(InterfaceMultiBus, Interface): def __init__(self, ifacename, pinspecs, ganged=None, single=False): Interface.__init__(self, ifacename, pinspecs, ganged, single) InterfaceMultiBus.__init__(self, self.pins) self.add_bus(True, ['ad_out', 'ad_out_en', 'ad_in'], - "Bit#({0})", "ad") + "Bit#({0})", "ad") self.add_bus(False, ['bwe', None, None], - "Bit#({0})", "bwe") + "Bit#({0})", "bwe") self.add_bus(False, ['tsiz', None, None], - "Bit#({0})", "tsiz") + "Bit#({0})", "tsiz") self.add_bus(False, ['cs', None, None], - "Bit#({0})", "cs") + "Bit#({0})", "cs") def ifacedef2(self, *args): return InterfaceMultiBus.ifacedef2(self, *args) + class InterfaceSD(InterfaceBus, Interface): def __init__(self, *args): @@ -562,6 +581,7 @@ class InterfaceSD(InterfaceBus, Interface): InterfaceBus.__init__(self, self.pins, True, ['out', 'out_en', 'in'], "Bit#({0})", "d") + class InterfaceNSPI(InterfaceBus, Interface): def __init__(self, *args): @@ -570,6 +590,7 @@ class InterfaceNSPI(InterfaceBus, Interface): ['io_out', 'io_out_en', 'io_in'], "Bit#({0})", "io") + class InterfaceEINT(Interface): """ uses old-style (non-get/put) for now """ @@ -592,6 +613,7 @@ class InterfaceGPIO(InterfaceBus, Interface): InterfaceBus.__init__(self, self.pins, True, ['out', 'out_en', 'in'], "Vector#({0},Bit#(1))", ifacename[-1]) + class Interfaces(InterfacesBase, PeripheralInterfaces): """ contains a list of interface definitions """ @@ -604,6 +626,7 @@ class Interfaces(InterfacesBase, PeripheralInterfaces): 'lcd': InterfaceLCD, 'sd': InterfaceSD, 'fb': InterfaceFlexBus, + 'sdr': InterfaceSDRAM, 'qspi': InterfaceNSPI, 'mqspi': InterfaceNSPI, 'eint': InterfaceEINT})