X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fperipheral_gen%2Fbase.py;h=53b5360b4de126901432f7683add55037ffe7c1b;hb=afc31db1d093e8427afec750191c65574ddeb1da;hp=ac508c47717d2304866f28314131f52767aa404c;hpb=9bb6a81d026880e798d6805b13b2f62a6aa4b8e2;p=pinmux.git

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index ac508c4..53b5360 100644
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -446,7 +446,7 @@ else"""
         return '\n'.join(ret)
 
     def mk_connection(self, name, count, fabricname, typ, name_override=None):
-        if name_override: # needed for GPIO
+        if name_override:  # needed for GPIO
             name = name_override
         print "PBase mk_conn", name, count
         ret = []
@@ -639,12 +639,12 @@ class PeripheralIface(object):
             return ('', 0)
         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 
-    def axi_fastaddr_map(self, count):
+    def axi_fastaddr_map(self, name, count):
         if not self.slow:
             return ''
         return self.slow.axi_fastaddr_map(self.ifacename, count)
 
-    def axi_addr_map(self, count):
+    def axi_addr_map(self, name, count):
         if not self.slow:
             return ''
         return self.slow.axi_addr_map(self.ifacename, count)
@@ -670,11 +670,13 @@ class PeripheralInterfaces(object):
         self.fastbusmode = False
 
         for (fname, kls, indent) in (
-                        ('_mk_connection', MkConnection, 8),
-                        ('_mk_pincon', MkPinCon, 4),
-                        ('_mk_clk_con', MkClkCon, 8),
-                        ('mk_ext_ifacedef', MkExtIface, 8),
-                        ):
+            ('_mk_connection', MkConnection, 8),
+            ('_mk_pincon', MkPinCon, 4),
+            ('_mk_clk_con', MkClkCon, 8),
+            ('mk_ext_ifacedef', MkExtIface, 8),
+            ('axi_addr_map', MkAxiAddrMap, 8),
+            ('axi_fastaddr_map', MkAxiFastAddrMap, 8),
+        ):
             fn = CallIfaceFn(self, kls, indent)
             setattr(self, fname, types.MethodType(fn, self))
 
@@ -798,24 +800,6 @@ class PeripheralInterfaces(object):
         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
                                  'fast', *args)
 
-    def axi_fastaddr_map(self, *args):
-        ret = []
-        for (name, count) in self.ifacecount:
-            for i in range(count):
-                if self.is_on_fastbus(name, i):
-                    continue
-                ret.append(self.data[name].axi_fastaddr_map(i))
-        return '\n'.join(li(list(filter(None, ret)), 8))
-
-    def axi_addr_map(self, *args):
-        ret = []
-        for (name, count) in self.ifacecount:
-            for i in range(count):
-                if self.is_on_fastbus(name, i):
-                    continue
-                ret.append(self.data[name].axi_addr_map(i))
-        return '\n'.join(li(list(filter(None, ret)), 8))
-
     def mkfast_peripheral(self, *args):
         ret = []
         for (name, count) in self.ifacecount:
@@ -953,7 +937,8 @@ class PeripheralInterfaces(object):
 
 class IfaceIter(object):
 
-    def __init__(self, name, count, *args):
+    def __init__(self, ifaces, name, count, *args):
+        self.ifaces = ifaces
         self.i = 0
         self.name = name
         self.maxcount = count
@@ -978,11 +963,26 @@ class IfaceIter(object):
     def next(self):
         return self.__next__()
 
-class MkConnection(IfaceIter):
 
-    def __init__(self, ifaces, name, count, *args):
-        self.ifaces = ifaces
-        IfaceIter.__init__(self, name, count, *args)
+class MkAxiFastAddrMap(IfaceIter):
+
+    def check(self, name, i):
+        return not self.ifaces.is_on_fastbus(name, i)
+
+    def item(self, name, i):
+        return self.ifaces.data[name].axi_fastaddr_map(name, i)
+
+
+class MkAxiAddrMap(IfaceIter):
+
+    def check(self, name, i):
+        return not self.ifaces.is_on_fastbus(name, i)
+
+    def item(self, name, i):
+        return self.ifaces.data[name].axi_addr_map(name, i)
+
+
+class MkConnection(IfaceIter):
 
     def check(self, name, i):
         return not self.ifaces.is_on_fastbus(name, i)
@@ -990,14 +990,11 @@ class MkConnection(IfaceIter):
     def item(self, name, i, fabric, typ, master):
         if master:
             return self.ifaces.data[name].mk_master_connection(name,
-                                i, fabric, typ)
+                                                               i, fabric, typ)
         return self.ifaces.data[name].mk_connection(name, i, fabric, typ)
 
-class MkExtIface(IfaceIter):
 
-    def __init__(self, ifaces, name, count, *args):
-        self.ifaces = ifaces
-        IfaceIter.__init__(self, name, count, *args)
+class MkExtIface(IfaceIter):
 
     def check(self, name, i):
         return not self.ifaces.is_on_fastbus(name, i)
@@ -1008,10 +1005,6 @@ class MkExtIface(IfaceIter):
 
 class MkPinCon(IfaceIter):
 
-    def __init__(self, ifaces, name, count, *args):
-        self.ifaces = ifaces
-        IfaceIter.__init__(self, name, count, *args)
-
     def check(self, name, i):
         return not self.ifaces.is_on_fastbus(name, i)
 
@@ -1021,10 +1014,6 @@ class MkPinCon(IfaceIter):
 
 class MkClkCon(IfaceIter):
 
-    def __init__(self, ifaces, name, count, *args):
-        self.ifaces = ifaces
-        IfaceIter.__init__(self, name, count, *args)
-
     def check(self, name, i):
         return not self.ifaces.is_on_fastbus(name, i)