X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fperipheral_gen%2Fbase.py;h=609e821f381be2df32daf952dbe05725e448b719;hb=76e4daaf6777cf0c8ea03d705484c7d367e38e5f;hp=fd5ef04cbeaae6e7659275f6fa9d36e6c8204675;hpb=f04f479c60c747ae9062bbd17aa92fa8002d0732;p=pinmux.git

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index fd5ef04..609e821 100644
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -76,6 +76,31 @@ class PBase(object):
     def slowimport(self):
         return ''
 
+    def get_mmap_configs(self):
+        res = []
+        for cfg in self.peripheral.configs:
+            res.append(cfg.get('mmap', None))
+        # XXX HACK!  assume all configs same for each peripheral!
+        return res[0]
+
+    def get_mmap_cfg_name(self, idx):
+        cfg = self.get_mmap_configs()
+        if cfg is None:
+            nregs = self.num_axi_regs32()
+            if isinstance(nregs, int) or len(nregs) == 1:
+                return ""
+            return "_%d_" % idx
+        return cfg[idx][0]
+
+    def num_axi_regs32cfg(self):
+        cfg = self.get_mmap_configs()
+        if cfg is None:
+            return self.num_axi_regs32()
+        regs = []
+        for c in cfg:
+            regs.append(c[2])
+        return regs
+
     def num_axi_regs32(self):
         return 0
 
@@ -102,12 +127,12 @@ class PBase(object):
         bname = self.axibase(name, ifacenum, idx)
         bend = self.axiend(name, ifacenum, idx)
         comment = "%d 32-bit regs" % numregs
-        return ("    `define %(bname)s 'h%(start)08X\n"
-                "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
+        return ("`define %(bname)s 'h%(start)08X\n"
+                "`define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
                 offs)
 
     def axi_reg_def(self, start, name, ifacenum):
-        offs = self.num_axi_regs32()
+        offs = self.num_axi_regs32cfg()
         if offs == 0:
             return ('', 0)
         if not isinstance(offs, list):
@@ -116,11 +141,8 @@ class PBase(object):
         offstotal = 0
         print offs
         for (idx, nregs) in enumerate(offs):
-            if len(offs) == 1:
-                idx = ""
-            else:
-                idx = "_%d_" % idx
-            (txt, off) = self._axi_reg_def(idx, nregs, start, name, ifacenum)
+            cfg = self.get_mmap_cfg_name(idx)
+            (txt, off) = self._axi_reg_def(cfg, nregs, start, name, ifacenum)
             start += off
             offstotal += off
             res.append(txt)
@@ -146,12 +168,9 @@ class PBase(object):
             offs = [offs]
         res = []
         for (i, nregs) in enumerate(offs):
-            if len(offs) == 1:
-                idx_ = ""
-            else:
-                idx_ = "_%d_" % i
-            name_ = self.axi_slave_name(idx_, name, ifacenum, typ)
-            res.append("typedef {0} {1};".format(idx+i, name_))
+            cfg = self.get_mmap_cfg_name(i)
+            name_ = self.axi_slave_name(cfg, name, ifacenum, typ)
+            res.append("typedef {0} {1};".format(idx + i, name_))
         return ('\n'.join(res), len(offs))
 
     def axi_fastaddr_map(self, name, ifacenum):
@@ -175,11 +194,8 @@ else"""
             offs = [offs]
         res = []
         for (idx, nregs) in enumerate(offs):
-            if len(offs) == 1:
-                idx = ""
-            else:
-                idx = "_%d_" % idx
-            res.append(self._axi_addr_map(idx, name, ifacenum, typ))
+            cfg = self.get_mmap_cfg_name(idx)
+            res.append(self._axi_addr_map(cfg, name, ifacenum, typ))
         return '\n'.join(res)
 
     def _mk_pincon(self, name, count, ptyp):
@@ -213,7 +229,7 @@ else"""
                     else:
                         ps_ = ps
                     cn = self._mk_actual_connection('out', name,
-                                                    count, typ, 
+                                                    count, typ,
                                                     pname, ps_, n_, fname)
                     ret += cn
                 fname = None
@@ -224,7 +240,7 @@ else"""
                         fname = "{0}.{1}".format(n_, fname)
                     fname = self.pinname_tweak(pname, 'outen', fname)
                     cn = self._mk_actual_connection('outen', name,
-                                                    count, typ, 
+                                                    count, typ,
                                                     pname, ps, n, fname)
                     ret += cn
             if typ == 'in' or typ == 'inout':
@@ -283,17 +299,16 @@ else"""
         elif ctype == 'in':
             if ck == PBase.get_clock_reset(self, name, count):
                 ret.append("mkConnection({1},\n\t\t\t{0});".format(
-                            ps, n))
+                    ps, n))
             else:
                 n2 = "{0}{1}".format(name, count)
                 sync = '{0}_{1}_sync'.format(n2, pname)
                 ret.append("mkConnection({1}.put,\n\t\t\t{0});".format(
-                            ps, sync))
+                    ps, sync))
                 ret.append("mkConnection({1},\n\t\t\t{0}.get);".format(
-                            sync, n))
+                    sync, n))
         return ret
 
-
     def _mk_clk_con(self, name, count, ctype):
         ret = []
         ck = self.get_clock_reset(name, count)
@@ -310,7 +325,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
         for p in self.peripheral.pinspecs:
             typ = p['type']
             pname = p['name']
-            n = name  
+            n = name
             if typ == 'out' or typ == 'inout':
                 fname = self.pinname_out(pname)
                 if not fname:
@@ -355,8 +370,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
         n_ = '{0}_{1}'.format(n_, pname)
         if typ == 'in' or typ == 'inout':
             ck, spc = spc, ck
-        return template.format(bitspec,  n_, ck, spc)
-
+        return template.format(bitspec, n_, ck, spc)
 
     def mk_cellconn(self, *args):
         return ''
@@ -383,7 +397,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
 
     def __mk_master_connection(self, con, aname, count, fabricname):
         txt = "mkConnection ({0}, {2}.v_from_masters\n" + \
-              "            [fromInteger(valueOf({1}))]);\n" 
+              "            [fromInteger(valueOf({1}))]);\n"
 
         print "PBase __mk_master_connection", self.name, aname
         if not con: