X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fperipheral_gen%2Fbase.py;h=e07ba18f299e13df887d18880133fa47d88396f7;hb=c370b2abc0b69f3f00220c579846f73cba9a4be9;hp=018015c06b0ac55784f2fd444f2addb039be26a1;hpb=3efb5c06f9926f2b6fdd851230e7fcc5d6a0a7ee;p=pinmux.git diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index 018015c..e07ba18 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -20,9 +20,56 @@ def li(txt, indent): return res -class PBase(object): +class MMapConfig(object): + + def get_mmap_configs(self): + res = [] + for cfg in self.peripheral.configs: + res.append(cfg.get('mmap', None)) + # XXX HACK! assume all configs same for each peripheral! + return res[0] + + def map_to_idx(self, cfg, idx): + if isinstance(idx, int): + return idx + for (i, c) in enumerate(cfg): + if c[0] == idx: + return i + assert "config name %s not found" % s + + def get_mmap_cfg_start(self, idx): + cfg = self.get_mmap_configs() + if cfg is None: + nregs = self.num_axi_regs32() + if isinstance(nregs, int) or len(nregs) == 1: + return 0 + return "_%d_" % idx + idx = self.map_to_idx(cfg, idx) + return cfg[idx][1] + + def get_mmap_cfg_name(self, idx): + cfg = self.get_mmap_configs() + if cfg is None: + nregs = self.num_axi_regs32() + if isinstance(nregs, int) or len(nregs) == 1: + return "" + return "_%d_" % idx + return cfg[idx][0] + + def num_axi_regs32cfg(self): + cfg = self.get_mmap_configs() + if cfg is None: + return self.num_axi_regs32() + regs = [] + for c in cfg: + regs.append(c[2]) + return regs + + +class PBase(MMapConfig): def __init__(self, name): self.name = name + MMapConfig.__init__(self) def extifdecl(self, name, count): sname = self.get_iname(count) @@ -85,56 +132,100 @@ class PBase(object): def get_iname(self, inum): return "{0}{1}".format(self.name, self.mksuffix(self.name, inum)) - def axibase(self, name, ifacenum): + def axibase(self, name, ifacenum, idx): name = name.upper() - return "%(name)s%(ifacenum)dBase" % locals() + return "%(name)s%(ifacenum)d%(idx)sBase" % locals() - def axiend(self, name, ifacenum): + def axiend(self, name, ifacenum, idx): name = name.upper() - return "%(name)s%(ifacenum)dEnd" % locals() + return "%(name)s%(ifacenum)d%(idx)sEnd" % locals() - def axi_reg_def(self, start, name, ifacenum): + def _axi_reg_def(self, idx, numregs, start, name, ifacenum): name = name.upper() - offs = self.num_axi_regs32() * 4 * 16 + offs = numregs * 4 * 16 if offs == 0: return ('', 0) - end = start + offs - 1 - bname = self.axibase(name, ifacenum) - bend = self.axiend(name, ifacenum) - comment = "%d 32-bit regs" % self.num_axi_regs32() - return (" `define %(bname)s 'h%(start)08X\n" - " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(), + cfgstart = self.get_mmap_cfg_start(idx) + if cfgstart: + start = cfgstart + end = start + offs - 1 + offs = 0 # don't do contiguous addressing + else: + end = start + offs - 1 + bname = self.axibase(name, ifacenum, idx) + bend = self.axiend(name, ifacenum, idx) + comment = "%d 32-bit regs" % numregs + return ("`define %(bname)s 'h%(start)08X\n" + "`define %(bend)s 'h%(end)08X // %(comment)s" % locals(), offs) + def axi_reg_def(self, start, name, ifacenum): + offs = self.num_axi_regs32cfg() + if offs == 0: + return ('', 0) + if not isinstance(offs, list): + offs = [offs] + res = [] + offstotal = 0 + print offs + for (idx, nregs) in enumerate(offs): + cfg = self.get_mmap_cfg_name(idx) + (txt, off) = self._axi_reg_def(cfg, nregs, start, name, ifacenum) + start += off + offstotal += off + res.append(txt) + return ('\n'.join(res), offstotal) + def axi_master_name(self, name, ifacenum, typ=''): name = name.upper() return "{0}{1}_master_num".format(name, ifacenum) - def axi_slave_name(self, name, ifacenum, typ=''): + def axi_slave_name(self, idx, name, ifacenum, typ=''): name = name.upper() - return "{0}{1}_{2}slave_num".format(name, ifacenum, typ) + return "{0}{1}{3}_{2}slave_num".format(name, ifacenum, typ, idx) def axi_master_idx(self, idx, name, ifacenum, typ): name = self.axi_master_name(name, ifacenum, typ) return ("typedef {0} {1};".format(idx, name), 1) def axi_slave_idx(self, idx, name, ifacenum, typ): - name = self.axi_slave_name(name, ifacenum, typ) - return ("typedef {0} {1};".format(idx, name), 1) + offs = self.num_axi_regs32() + if offs == 0: + return '' + if not isinstance(offs, list): + offs = [offs] + res = [] + for (i, nregs) in enumerate(offs): + cfg = self.get_mmap_cfg_name(i) + name_ = self.axi_slave_name(cfg, name, ifacenum, typ) + res.append("typedef {0} {1};".format(idx + i, name_)) + return ('\n'.join(res), len(offs)) def axi_fastaddr_map(self, name, ifacenum): return self.axi_addr_map(name, ifacenum, 'fast') - def axi_addr_map(self, name, ifacenum, typ=""): - bname = self.axibase(name, ifacenum) - bend = self.axiend(name, ifacenum) - name = self.axi_slave_name(name, ifacenum, typ) + def _axi_addr_map(self, idx, name, ifacenum, typ=""): + bname = self.axibase(name, ifacenum, idx) + bend = self.axiend(name, ifacenum, idx) + name = self.axi_slave_name(idx, name, ifacenum, typ) template = """\ if(addr>=`{0} && addr<=`{1}) return tuple2(True,fromInteger(valueOf({2}))); else""" return template.format(bname, bend, name) + def axi_addr_map(self, name, ifacenum, typ=""): + offs = self.num_axi_regs32() + if offs == 0: + return '' + if not isinstance(offs, list): + offs = [offs] + res = [] + for (idx, nregs) in enumerate(offs): + cfg = self.get_mmap_cfg_name(idx) + res.append(self._axi_addr_map(cfg, name, ifacenum, typ)) + return '\n'.join(res) + def _mk_pincon(self, name, count, ptyp): # TODO: really should be using bsv.interface_decl.Interfaces # pin-naming rules.... logic here is hard-coded to duplicate @@ -166,7 +257,7 @@ else""" else: ps_ = ps cn = self._mk_actual_connection('out', name, - count, typ, + count, typ, pname, ps_, n_, fname) ret += cn fname = None @@ -177,7 +268,7 @@ else""" fname = "{0}.{1}".format(n_, fname) fname = self.pinname_tweak(pname, 'outen', fname) cn = self._mk_actual_connection('outen', name, - count, typ, + count, typ, pname, ps, n, fname) ret += cn if typ == 'in' or typ == 'inout': @@ -236,17 +327,16 @@ else""" elif ctype == 'in': if ck == PBase.get_clock_reset(self, name, count): ret.append("mkConnection({1},\n\t\t\t{0});".format( - ps, n)) + ps, n)) else: n2 = "{0}{1}".format(name, count) sync = '{0}_{1}_sync'.format(n2, pname) ret.append("mkConnection({1}.put,\n\t\t\t{0});".format( - ps, sync)) + ps, sync)) ret.append("mkConnection({1},\n\t\t\t{0}.get);".format( - sync, n)) + sync, n)) return ret - def _mk_clk_con(self, name, count, ctype): ret = [] ck = self.get_clock_reset(name, count) @@ -263,7 +353,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( for p in self.peripheral.pinspecs: typ = p['type'] pname = p['name'] - n = name + n = name if typ == 'out' or typ == 'inout': fname = self.pinname_out(pname) if not fname: @@ -308,8 +398,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( n_ = '{0}_{1}'.format(n_, pname) if typ == 'in' or typ == 'inout': ck, spc = spc, ck - return template.format(bitspec, n_, ck, spc) - + return template.format(bitspec, n_, ck, spc) def mk_cellconn(self, *args): return '' @@ -323,7 +412,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( def mksuffix(self, name, i): return i - def __mk_connection(self, con, aname, fabricname): + def __mk_connection(self, con, aname, count, fabricname): txt = "mkConnection ({2}.v_to_slaves\n" + \ " [fromInteger(valueOf({1}))],\n" + \ " {0});" @@ -331,15 +420,17 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( print "PBase __mk_connection", self.name, aname if not con: return '' + con = con.format(count, aname) return txt.format(con, aname, fabricname) - def __mk_master_connection(self, con, aname, fabricname): + def __mk_master_connection(self, con, aname, count, fabricname): txt = "mkConnection ({0}, {2}.v_from_masters\n" + \ - " [fromInteger(valueOf({1}))]);\n" + " [fromInteger(valueOf({1}))]);\n" print "PBase __mk_master_connection", self.name, aname if not con: return '' + con = con.format(count, aname) return txt.format(con, aname, fabricname) def mk_master_connection(self, count, fabricname, typ, name=None): @@ -349,16 +440,28 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( name = self.name print "PBase mk_master_conn", self.name, count aname = self.axi_master_name(name, count, typ) - con = self._mk_connection(name, count, True).format(count, aname) - return self.__mk_master_connection(con, aname, fabricname) + ret = [] + connections = self._mk_connection(name, count, True) + if not isinstance(connections, list): + connections = [connections] + for con in connections: + ret.append(self.__mk_master_connection(con, aname, count, + fabricname)) + return '\n'.join(ret) def mk_connection(self, count, fabricname, typ, name=None): if name is None: name = self.name print "PBase mk_conn", self.name, count - aname = self.axi_slave_name(name, count, typ) - con = self._mk_connection(name, count).format(count, aname) - return self.__mk_connection(con, aname, fabricname) + ret = [] + connections = self._mk_connection(name, count) + if not isinstance(connections, list): + connections = [connections] + for (idx, con) in enumerate(connections): + cfg = self.get_mmap_cfg_name(idx) + aname = self.axi_slave_name(cfg, name, count, typ) + ret.append(self.__mk_connection(con, aname, count, fabricname)) + return '\n'.join(ret) def _mk_connection(self, name=None, count=0): return '' @@ -893,10 +996,12 @@ class PFactory(object): from gpio import gpio from rgbttl import rgbttl from flexbus import flexbus + from sdram import sdram for k, v in {'uart': uart, 'rs232': rs232, 'twi': twi, + 'sdr': sdram, 'quart': quart, 'mqspi': mqspi, 'mspi': mspi, @@ -904,7 +1009,7 @@ class PFactory(object): 'spi': spi, 'pwm': pwm, 'eint': eint, - 'sd': sdmmc, + 'mmc': sdmmc, 'jtag': jtag, 'lcd': rgbttl, 'fb': flexbus,