X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fperipheral_gen%2Fbase.py;h=e07ba18f299e13df887d18880133fa47d88396f7;hb=c370b2abc0b69f3f00220c579846f73cba9a4be9;hp=ed9fe4f62c149aa17239b6b404d026b949a0f03f;hpb=7d228e93162f27de9945b133908f1d55e10d40ea;p=pinmux.git diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index ed9fe4f..e07ba18 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -20,9 +20,56 @@ def li(txt, indent): return res -class PBase(object): +class MMapConfig(object): + + def get_mmap_configs(self): + res = [] + for cfg in self.peripheral.configs: + res.append(cfg.get('mmap', None)) + # XXX HACK! assume all configs same for each peripheral! + return res[0] + + def map_to_idx(self, cfg, idx): + if isinstance(idx, int): + return idx + for (i, c) in enumerate(cfg): + if c[0] == idx: + return i + assert "config name %s not found" % s + + def get_mmap_cfg_start(self, idx): + cfg = self.get_mmap_configs() + if cfg is None: + nregs = self.num_axi_regs32() + if isinstance(nregs, int) or len(nregs) == 1: + return 0 + return "_%d_" % idx + idx = self.map_to_idx(cfg, idx) + return cfg[idx][1] + + def get_mmap_cfg_name(self, idx): + cfg = self.get_mmap_configs() + if cfg is None: + nregs = self.num_axi_regs32() + if isinstance(nregs, int) or len(nregs) == 1: + return "" + return "_%d_" % idx + return cfg[idx][0] + + def num_axi_regs32cfg(self): + cfg = self.get_mmap_configs() + if cfg is None: + return self.num_axi_regs32() + regs = [] + for c in cfg: + regs.append(c[2]) + return regs + + +class PBase(MMapConfig): def __init__(self, name): self.name = name + MMapConfig.__init__(self) def extifdecl(self, name, count): sname = self.get_iname(count) @@ -76,30 +123,6 @@ class PBase(object): def slowimport(self): return '' - def get_mmap_configs(self): - res = [] - for cfg in self.peripheral.configs: - res.append(cfg.get('mmap', None)) - return res[0] # XXX HACK! assume all configs same for each peripheral! - - def get_mmap_cfg_name(self, idx): - cfg = self.get_mmap_configs() - if cfg is None: - nregs = self.num_axi_regs32() - if isinstance(nregs, int) or len(nregs) == 1: - return "" - return "_%d_" % idx - return cfg[idx][0] - - def num_axi_regs32cfg(self): - cfg = self.get_mmap_configs() - if cfg is None: - return self.num_axi_regs32() - regs = [] - for c in cfg: - regs.append(c[2]) - return regs - def num_axi_regs32(self): return 0 @@ -122,12 +145,18 @@ class PBase(object): offs = numregs * 4 * 16 if offs == 0: return ('', 0) - end = start + offs - 1 + cfgstart = self.get_mmap_cfg_start(idx) + if cfgstart: + start = cfgstart + end = start + offs - 1 + offs = 0 # don't do contiguous addressing + else: + end = start + offs - 1 bname = self.axibase(name, ifacenum, idx) bend = self.axiend(name, ifacenum, idx) comment = "%d 32-bit regs" % numregs - return (" `define %(bname)s 'h%(start)08X\n" - " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(), + return ("`define %(bname)s 'h%(start)08X\n" + "`define %(bend)s 'h%(end)08X // %(comment)s" % locals(), offs) def axi_reg_def(self, start, name, ifacenum): @@ -169,7 +198,7 @@ class PBase(object): for (i, nregs) in enumerate(offs): cfg = self.get_mmap_cfg_name(i) name_ = self.axi_slave_name(cfg, name, ifacenum, typ) - res.append("typedef {0} {1};".format(idx+i, name_)) + res.append("typedef {0} {1};".format(idx + i, name_)) return ('\n'.join(res), len(offs)) def axi_fastaddr_map(self, name, ifacenum): @@ -228,7 +257,7 @@ else""" else: ps_ = ps cn = self._mk_actual_connection('out', name, - count, typ, + count, typ, pname, ps_, n_, fname) ret += cn fname = None @@ -239,7 +268,7 @@ else""" fname = "{0}.{1}".format(n_, fname) fname = self.pinname_tweak(pname, 'outen', fname) cn = self._mk_actual_connection('outen', name, - count, typ, + count, typ, pname, ps, n, fname) ret += cn if typ == 'in' or typ == 'inout': @@ -298,17 +327,16 @@ else""" elif ctype == 'in': if ck == PBase.get_clock_reset(self, name, count): ret.append("mkConnection({1},\n\t\t\t{0});".format( - ps, n)) + ps, n)) else: n2 = "{0}{1}".format(name, count) sync = '{0}_{1}_sync'.format(n2, pname) ret.append("mkConnection({1}.put,\n\t\t\t{0});".format( - ps, sync)) + ps, sync)) ret.append("mkConnection({1},\n\t\t\t{0}.get);".format( - sync, n)) + sync, n)) return ret - def _mk_clk_con(self, name, count, ctype): ret = [] ck = self.get_clock_reset(name, count) @@ -325,7 +353,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( for p in self.peripheral.pinspecs: typ = p['type'] pname = p['name'] - n = name + n = name if typ == 'out' or typ == 'inout': fname = self.pinname_out(pname) if not fname: @@ -370,8 +398,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( n_ = '{0}_{1}'.format(n_, pname) if typ == 'in' or typ == 'inout': ck, spc = spc, ck - return template.format(bitspec, n_, ck, spc) - + return template.format(bitspec, n_, ck, spc) def mk_cellconn(self, *args): return '' @@ -398,7 +425,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( def __mk_master_connection(self, con, aname, count, fabricname): txt = "mkConnection ({0}, {2}.v_from_masters\n" + \ - " [fromInteger(valueOf({1}))]);\n" + " [fromInteger(valueOf({1}))]);\n" print "PBase __mk_master_connection", self.name, aname if not con: @@ -431,11 +458,8 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( if not isinstance(connections, list): connections = [connections] for (idx, con) in enumerate(connections): - if len(connections) == 1: - idx = "" - else: - idx = "_%d_" % idx - aname = self.axi_slave_name(idx, name, count, typ) + cfg = self.get_mmap_cfg_name(idx) + aname = self.axi_slave_name(cfg, name, count, typ) ret.append(self.__mk_connection(con, aname, count, fabricname)) return '\n'.join(ret)