X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fperipheral_gen%2Fsdram.py;h=c053ed02c67c5cb67985b0c8192015c12dcb7104;hb=92cd44bcd9a90ea2f1eb0f49c9a498fde092f331;hp=b676933eb4c5f4d51ce2f8cb236b8ab8cdbe1327;hpb=21924054a7c9ca826d0fc047bb1501dfda425506;p=pinmux.git

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index b676933..c053ed0 100644
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -4,38 +4,36 @@ from bsv.peripheral_gen.base import PBase
 class sdram(PBase):
 
     def slowimport(self):
-        return "import FlexBus_Types::*;"
+        return "import sdr_top::*;"
 
     def num_axi_regs32(self):
-        return 0x400000  # defines an entire memory range
+        return [0x400000,  # defines an entire memory range (hack...)
+                12]        # defines the number of configuration regs
 
     def extfastifinstance(self, name, count):
         return "// TODO" + self._extifinstance(name, count, "_out", "", True,
-                                   ".sdram_side")
+                                   ".if_sdram_out")
 
     def fastifdecl(self, name, count):
-        return "//interface FlexBus_Master_IFC sdr{0}_out;".format(count)
+        return "// (*always_ready*) interface " + \
+                "Ifc_sdram_out sdr{0}_out;".format(count)
 
     def get_clock_reset(self, name, count):
         return "slow_clock, slow_reset"
 
     def mkfast_peripheral(self):
-        return "AXI4_Slave_to_FlexBus_Master_Xactor_IFC " + \
-               "#(`PADDR, `DATA, `USERSPACE)\n" + \
-               "        sdr{0} <- mkAXI4_Slave_to_FlexBus_Master_Xactor;"
+        return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
 
     def _mk_connection(self, name=None, count=0):
-        return "sdr{0}.axi_side"
-
-    def pinname_in(self, pname):
-        return {'ta': 'sdram_side.m_tAn',
-                }.get(pname, '')
-
+        return ["sdr{0}.axi4_slave_sdram",
+                "sdr{0}.axi4_slave_cntrl_reg"]
+                
     def pinname_out(self, pname):
-        return {'ale': 'sdram_side.m_ALE',
-                'oe': 'sdram_side.m_OEn',
-                'tbst': 'sdram_side.m_TBSTn',
-                'rw': 'sdram_side.m_R_Wn',
+        return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
+                'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
+                'sdrcke': 'ifc_sdram_out.osdr_cke',
+                'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
+                'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
                 }.get(pname, '')
 
     def _mk_clk_con(self, name, count, ctype):
@@ -57,14 +55,14 @@ class sdram(PBase):
         ret = [PBase._mk_pincon(self, name, count, typ)]
         assert typ == 'fast' # TODO slow?
         for pname, stype, ptype in [
-            ('cs', 'm_FBCSn', 'out'),
-            ('bwe', 'm_BWEn', 'out'),
-            ('tsiz', 'm_TSIZ', 'out'),
-            ('ad_out', 'm_AD', 'out'),
-            ('ad_in', 'm_din', 'in'),
-            ('ad_out_en', 'm_OE32n', 'out'),
+            ('sdrdqm', 'osdr_dqm', 'out'),
+            ('sdrba', 'osdr_ba', 'out'),
+            ('sdrad', 'osdr_addr', 'out'),
+            ('sdrd_out', 'osdr_dout', 'out'),
+            ('sdrd_in', 'ipad_sdr_din', 'in'),
+            ('sdrd_out_en', 'osdr_den_n', 'out'),
         ]:
             ret.append(self._mk_vpincon(name, count, typ, ptype, pname,
-                                        "sdram_side.{0}".format(stype)))
+                                        "ifc_sdram_out.{0}".format(stype)))
 
         return '\n'.join(ret)