X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fperipheral_gen%2Fsdram.py;h=ce6ba4364e43fd3492b531e64389c13434afa2fa;hb=1a80bda82b1f3541f83b7d3e11397e2299e8da63;hp=baf355d0dc455de0770d51ccbc9604fa7738716a;hpb=37d8ffef907fe56bca284e6ccbafb4ea1f2c6437;p=pinmux.git

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index baf355d..ce6ba43 100644
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -4,49 +4,51 @@ from bsv.peripheral_gen.base import PBase
 class sdram(PBase):
 
     def slowimport(self):
-        return "import FlexBus_Types::*;"
+        return "import sdr_top::*;"
 
     def num_axi_regs32(self):
-        return 0x400000  # defines an entire memory range
+        return [0x400000,  # defines an entire memory range (hack...)
+                12]        # defines the number of configuration regs
 
     def extfastifinstance(self, name, count):
         return "// TODO" + self._extifinstance(name, count, "_out", "", True,
-                                   ".sdram_side")
+                                   ".if_sdram_out")
 
     def fastifdecl(self, name, count):
-        return "//interface FlexBus_Master_IFC fb{0}_out;".format(count)
+        return "// (*always_ready*) interface " + \
+                "Ifc_sdram_out sdr{0}_out;".format(count)
+
+    def get_clk_spc(self, typ):
+        return "clk0, slow_reset"
 
     def get_clock_reset(self, name, count):
         return "slow_clock, slow_reset"
 
     def mkfast_peripheral(self):
-        return "AXI4_Slave_to_FlexBus_Master_Xactor_IFC " + \
-               "#(`PADDR, `DATA, `USERSPACE)\n" + \
-               "        fb{0} <- mkAXI4_Slave_to_FlexBus_Master_Xactor;"
+        return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
 
     def _mk_connection(self, name=None, count=0):
-        return "fb{0}.axi_side"
-
-    def pinname_in(self, pname):
-        return {'ta': 'sdram_side.m_tAn',
-                }.get(pname, '')
-
+        return ["sdr{0}.axi4_slave_sdram",
+                "sdr{0}.axi4_slave_cntrl_reg"]
+                
     def pinname_out(self, pname):
-        return {'ale': 'sdram_side.m_ALE',
-                'oe': 'sdram_side.m_OEn',
-                'tbst': 'sdram_side.m_TBSTn',
-                'rw': 'sdram_side.m_R_Wn',
+        return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
+                'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
+                'sdrcke': 'ifc_sdram_out.osdr_cke',
+                'sdrclk': 'ifc_sdram_out.osdr_clock',
+                'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
+                'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
                 }.get(pname, '')
 
     def _mk_clk_con(self, name, count, ctype):
         ret = [PBase._mk_clk_con(self, name, count, ctype)]
         for pname, sz, ptype in [
-            ('cs', 6, 'out'),
-            ('bwe', 4, 'out'),
-            ('tsiz', 2, 'out'),
-            ('ad_out', 32, 'out'),
-            ('ad_in', 32, 'in'),
-            ('ad_out_en', 32, 'out'),
+            ('dqm', 8, 'out'),
+            ('ba', 2, 'out'),
+            ('ad', 13, 'out'),
+            ('d_out', 64, 'out'),
+            ('d_in', 64, 'in'),
+            ('d_out_en', 64, 'out'),
         ]:
             bitspec = "Bit#(%d)" % sz
             txt = self._mk_clk_vcon(name, count, ctype, ptype, pname, bitspec)
@@ -57,14 +59,14 @@ class sdram(PBase):
         ret = [PBase._mk_pincon(self, name, count, typ)]
         assert typ == 'fast' # TODO slow?
         for pname, stype, ptype in [
-            ('cs', 'm_FBCSn', 'out'),
-            ('bwe', 'm_BWEn', 'out'),
-            ('tsiz', 'm_TSIZ', 'out'),
-            ('ad_out', 'm_AD', 'out'),
-            ('ad_in', 'm_din', 'in'),
-            ('ad_out_en', 'm_OE32n', 'out'),
+            ('dqm', 'osdr_dqm', 'out'),
+            ('ba', 'osdr_ba', 'out'),
+            ('ad', 'osdr_addr', 'out'),
+            ('d_out', 'osdr_dout', 'out'),
+            ('d_in', 'ipad_sdr_din', 'in'),
+            ('d_out_en', 'osdr_den_n', 'out'),
         ]:
             ret.append(self._mk_vpincon(name, count, typ, ptype, pname,
-                                        "sdram_side.{0}".format(stype)))
+                                        "ifc_sdram_out.{0}".format(stype)))
 
         return '\n'.join(ret)