X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fpinmux_generator.py;h=64ab8851b071b8fc8bb64a945056d1fd96f4f2f0;hb=0e07cd1c35e098cac02d0278ed18f1e3d8090352;hp=5683b0057f35986dbddf949afa5f13f1083f7b3a;hpb=0fa2d88cb2f23eca6b3d57362c6e064ae8fe9334;p=pinmux.git diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 5683b00..64ab885 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -81,7 +81,6 @@ def pinmuxgen(pth=None, verify=True): bus = os.path.join(bp, 'busenable.bsv') pmp = os.path.join(bp, 'pinmux.bsv') - ptp = os.path.join(bp, 'PinTop.bsv') bvp = os.path.join(bp, 'bus.bsv') idef = os.path.join(bp, 'instance_defines.bsv') slow = os.path.join(bp, 'slow_peripherals.bsv') @@ -94,7 +93,6 @@ def pinmuxgen(pth=None, verify=True): soct = os.path.join(cwd, 'soc_template.bsv') write_pmp(pmp, p, ifaces, iocells) - write_ptp(ptp, p, ifaces) write_bvp(bvp, p, ifaces) write_bus(bus, p, ifaces) write_instances(idef, p, ifaces) @@ -121,6 +119,7 @@ def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells): numsloirqs = ifaces.mk_sloirqsdef() ifacedef = ifaces.mk_ext_ifacedef() ifacedef = ifaces.mk_ext_ifacedef() + clockcon = ifaces.mk_slowclk_con() with open(slow, "w") as bsv_file: with open(slowt) as f: @@ -129,7 +128,7 @@ def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells): fnaddrmap, mkslow, mkcon, mkcellcon, pincon, inst, mkplic, numsloirqs, ifacedef, - inst2)) + inst2, clockcon)) with open(slowmf, "w") as bsv_file: with open(slowmt) as f: @@ -151,14 +150,16 @@ def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells): fnaddrmap = ifaces.axi_fastaddr_map() mkfast = ifaces.mkfast_peripheral() mkcon = ifaces.mk_fast_connection() + mkmstcon = ifaces.mk_master_connection() mkcellcon = ifaces.mk_cellconn() - pincon = ifaces.mk_pincon() + pincon = ifaces.mk_fast_pincon() inst = ifaces.extfastifinstance() mkplic = ifaces.mk_plic() numsloirqs = ifaces.mk_sloirqsdef() ifacedef = ifaces.mk_ext_ifacedef() dma = ifaces.mk_dma_irq() num_dmachannels = ifaces.num_dmachannels() + clockcon = ifaces.mk_fastclk_con() with open(soc, "w") as bsv_file: with open(soct) as f: @@ -167,6 +168,7 @@ def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells): slavedecl, mastdecl, mkcon, inst, dma, num_dmachannels, pincon, regdef, fnaddrmap, + clockcon, mkmstcon, )) with open(fastmf, "w") as bsv_file: @@ -188,7 +190,7 @@ def write_pmp(pmp, p, ifaces, iocells): with open(pmp, "w") as bsv_file: bsv_file.write(header) - cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth + bwid_template = 'Bit#(%d)' bsv_file.write('''\ (*always_ready,always_enabled*) interface MuxSelectionLines; @@ -199,7 +201,12 @@ def write_pmp(pmp, p, ifaces, iocells): // where each IO will have the same number of muxes.''') for cell in p.muxed_cells: - bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width)) + cellnum = cell[0] + bitwidth = p.get_muxbitwidth(cellnum) + if bitwidth == 0: + continue + cell_bit_width = bwid_template % bitwidth + bsv_file.write(mux_interface.ifacefmt(cellnum, cell_bit_width)) bsv_file.write("\n endinterface\n") @@ -271,8 +278,12 @@ def write_pmp(pmp, p, ifaces, iocells): // values for each mux assigned to a CELL ''') for cell in p.muxed_cells: - bsv_file.write(mux_interface.wirefmt( - cell[0], cell_bit_width)) + cellnum = cell[0] + bitwidth = p.get_muxbitwidth(cellnum) + if bitwidth == 0: + continue + cell_bit_width = bwid_template % bitwidth + bsv_file.write(mux_interface.wirefmt(cellnum, cell_bit_width)) iocells.wirefmt(bsv_file) ifaces.wirefmt(bsv_file) @@ -294,9 +305,14 @@ def write_pmp(pmp, p, ifaces, iocells): interface mux_lines = interface MuxSelectionLines ''') for cell in p.muxed_cells: + cellnum = cell[0] + bitwidth = p.get_muxbitwidth(cellnum) + if bitwidth == 0: + continue + cell_bit_width = bwid_template % bitwidth bsv_file.write( mux_interface.ifacedef( - cell[0], cell_bit_width)) + cellnum, cell_bit_width)) bsv_file.write("\n endinterface;") bsv_file.write(''' @@ -318,82 +334,6 @@ def write_pmp(pmp, p, ifaces, iocells): # ====================================================================== -def write_ptp(ptp, p, ifaces): - with open(ptp, 'w') as bsv_file: - bsv_file.write(copyright + ''' -package PinTop; - import pinmux::*; - interface Ifc_PintTop; - method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data); - method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr); - interface PeripheralSide peripheral_side; - endinterface - - module mkPinTop(Ifc_PintTop); - // instantiate the pin-mux module here - Ifc_pinmux pinmux <-mkpinmux; - - // declare the registers which will be used to mux the IOs -'''.format(p.ADDR_WIDTH, p.DATA_WIDTH)) - - cell_bit_width = str(p.cell_bitwidth) - for cell in p.muxed_cells: - bsv_file.write(''' - Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format( - cell_bit_width, cell[0])) - - bsv_file.write(''' - // rule to connect the registers to the selection lines of the - // pin-mux module - rule connect_selection_registers;''') - - for cell in p.muxed_cells: - bsv_file.write(''' - pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0])) - - bsv_file.write(''' - endrule - // method definitions for the write user interface - method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data); - Bool err=False; - case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset, - p.ADDR_WIDTH, p.DATA_WIDTH)) - index = 0 - for cell in p.muxed_cells: - bsv_file.write(''' - {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0])) - index = index + 1 - - bsv_file.write(''' - default: err=True; - endcase - return err; - endmethod''') - - bsv_file.write(''' - // method definitions for the read user interface - method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr); - Bool err=False; - Bit#(32) data=0; - case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset, - p.ADDR_WIDTH, p.DATA_WIDTH)) - index = 0 - for cell in p.muxed_cells: - bsv_file.write(''' - {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0])) - index = index + 1 - - bsv_file.write(''' - default:err=True; - endcase - return tuple2(err,data); - endmethod - interface peripheral_side=pinmux.peripheral_side; - endmodule -endpackage -''') - - def write_bvp(bvp, p, ifaces): # ######## Generate bus transactors ################ gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \ @@ -443,11 +383,11 @@ def write_instances(idef, p, ifaces): with open(idef, 'w') as bsv_file: txt = '''\ `define ADDR {0} -`define PADDR {0} +`define PADDR {2} `define DATA {1} `define Reg_width {1} `define USERSPACE 0 -//`define RV64 +`define RV64 // TODO: work out if these are needed `define PWM_AXI4Lite @@ -473,4 +413,6 @@ def write_instances(idef, p, ifaces): `define BAUD_RATE 5 //130 // `endif ''' - bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH)) + bsv_file.write(txt.format(p.ADDR_WIDTH, + p.DATA_WIDTH, + p.PADDR_WIDTH))