X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fbsv%2Fpinmux_generator.py;h=bcc1b254cb9b0a5a5d5582fb3eb8d3bcd3057eea;hb=8c41066184b2196a45421619d98ba0be890a1c05;hp=12c281311664893e11fa7d459f74b5474d92bc98;hpb=48993171d8f12bd30d5921e86310248d343ef151;p=pinmux.git diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 12c2813..bcc1b25 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -81,29 +81,29 @@ def pinmuxgen(pth=None, verify=True): bus = os.path.join(bp, 'busenable.bsv') pmp = os.path.join(bp, 'pinmux.bsv') - ptp = os.path.join(bp, 'PinTop.bsv') bvp = os.path.join(bp, 'bus.bsv') idef = os.path.join(bp, 'instance_defines.bsv') slow = os.path.join(bp, 'slow_peripherals.bsv') slowt = os.path.join(cwd, 'slow_peripherals_template.bsv') - soc = os.path.join(bp, 'soc.bsv') + slowmf = os.path.join(bp, 'slow_memory_map.bsv') + slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv') + fastmf = os.path.join(bp, 'fast_memory_map.bsv') + fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv') + soc = os.path.join(bp, 'socgen.bsv') soct = os.path.join(cwd, 'soc_template.bsv') write_pmp(pmp, p, ifaces, iocells) - write_ptp(ptp, p, ifaces) write_bvp(bvp, p, ifaces) write_bus(bus, p, ifaces) write_instances(idef, p, ifaces) - write_slow(slow, slowt, p, ifaces, iocells) - write_soc(soc, soct, p, ifaces, iocells) + write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells) + write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells) -def write_slow(slow, slowt, p, ifaces, iocells): +def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells): """ write out the slow_peripherals.bsv file. joins all the peripherals together into one AXI Lite interface """ - with open(slowt) as bsv_file: - slowt = bsv_file.read() imports = ifaces.slowimport() ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl() regdef = ifaces.axi_reg_def() @@ -119,45 +119,63 @@ def write_slow(slow, slowt, p, ifaces, iocells): numsloirqs = ifaces.mk_sloirqsdef() ifacedef = ifaces.mk_ext_ifacedef() ifacedef = ifaces.mk_ext_ifacedef() + clockcon = ifaces.mk_slowclk_con() + with open(slow, "w") as bsv_file: + with open(slowt) as f: + slowt = f.read() bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl, fnaddrmap, mkslow, mkcon, mkcellcon, pincon, inst, mkplic, numsloirqs, ifacedef, - inst2)) + inst2, clockcon)) + + with open(slowmf, "w") as bsv_file: + with open(slowmt) as f: + slowmt = f.read() + bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap)) -def write_soc(soc, soct, p, ifaces, iocells): +def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells): """ write out the soc.bsv file. joins all the peripherals together as AXI Masters """ ifaces.fastbusmode = True # side-effects... shouldn't really do this - with open(soct) as bsv_file: - soct = bsv_file.read() + imports = ifaces.slowimport() ifdecl = ifaces.fastifdecl() -#ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl() - regdef = ifaces.axi_reg_def() + regdef = ifaces.axi_fastmem_def() slavedecl = ifaces.axi_fastslave_idx() mastdecl = ifaces.axi_master_idx() - fnaddrmap = ifaces.axi_addr_map() + fnaddrmap = ifaces.axi_fastaddr_map() mkfast = ifaces.mkfast_peripheral() mkcon = ifaces.mk_fast_connection() + mkmstcon = ifaces.mk_master_connection() mkcellcon = ifaces.mk_cellconn() - pincon = ifaces.mk_pincon() + pincon = ifaces.mk_fast_pincon() inst = ifaces.extfastifinstance() mkplic = ifaces.mk_plic() numsloirqs = ifaces.mk_sloirqsdef() ifacedef = ifaces.mk_ext_ifacedef() dma = ifaces.mk_dma_irq() num_dmachannels = ifaces.num_dmachannels() + clockcon = ifaces.mk_fastclk_con() + with open(soc, "w") as bsv_file: + with open(soct) as f: + soct = f.read() bsv_file.write(soct.format(imports, ifdecl, mkfast, slavedecl, mastdecl, mkcon, inst, dma, num_dmachannels, - pincon, + pincon, regdef, fnaddrmap, + clockcon, mkmstcon, )) + with open(fastmf, "w") as bsv_file: + with open(fastmt) as f: + fastmt = f.read() + bsv_file.write(fastmt.format(regdef, slavedecl, mastdecl, fnaddrmap)) + def write_bus(bus, p, ifaces): # package and interface declaration followed by @@ -302,82 +320,6 @@ def write_pmp(pmp, p, ifaces, iocells): # ====================================================================== -def write_ptp(ptp, p, ifaces): - with open(ptp, 'w') as bsv_file: - bsv_file.write(copyright + ''' -package PinTop; - import pinmux::*; - interface Ifc_PintTop; - method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data); - method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr); - interface PeripheralSide peripheral_side; - endinterface - - module mkPinTop(Ifc_PintTop); - // instantiate the pin-mux module here - Ifc_pinmux pinmux <-mkpinmux; - - // declare the registers which will be used to mux the IOs -'''.format(p.ADDR_WIDTH, p.DATA_WIDTH)) - - cell_bit_width = str(p.cell_bitwidth) - for cell in p.muxed_cells: - bsv_file.write(''' - Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format( - cell_bit_width, cell[0])) - - bsv_file.write(''' - // rule to connect the registers to the selection lines of the - // pin-mux module - rule connect_selection_registers;''') - - for cell in p.muxed_cells: - bsv_file.write(''' - pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0])) - - bsv_file.write(''' - endrule - // method definitions for the write user interface - method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data); - Bool err=False; - case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset, - p.ADDR_WIDTH, p.DATA_WIDTH)) - index = 0 - for cell in p.muxed_cells: - bsv_file.write(''' - {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0])) - index = index + 1 - - bsv_file.write(''' - default: err=True; - endcase - return err; - endmethod''') - - bsv_file.write(''' - // method definitions for the read user interface - method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr); - Bool err=False; - Bit#(32) data=0; - case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset, - p.ADDR_WIDTH, p.DATA_WIDTH)) - index = 0 - for cell in p.muxed_cells: - bsv_file.write(''' - {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0])) - index = index + 1 - - bsv_file.write(''' - default:err=True; - endcase - return tuple2(err,data); - endmethod - interface peripheral_side=pinmux.peripheral_side; - endmodule -endpackage -''') - - def write_bvp(bvp, p, ifaces): # ######## Generate bus transactors ################ gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \ @@ -427,10 +369,11 @@ def write_instances(idef, p, ifaces): with open(idef, 'w') as bsv_file: txt = '''\ `define ADDR {0} -`define PADDR {0} +`define PADDR {2} `define DATA {1} `define Reg_width {1} `define USERSPACE 0 +`define RV64 // TODO: work out if these are needed `define PWM_AXI4Lite @@ -441,6 +384,11 @@ def write_instances(idef, p, ifaces): `define PERFMONITORS 64 `define DCACHE_WAYS 4 `define DCACHE_TAG_BITS 20 // tag_bits = 52 + +// CLINT + `define ClintBase 'h02000000 + `define ClintEnd 'h020BFFFF + `define PLIC `define PLICBase 'h0c000000 `define PLICEnd 'h10000000 @@ -451,4 +399,6 @@ def write_instances(idef, p, ifaces): `define BAUD_RATE 5 //130 // `endif ''' - bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH)) + bsv_file.write(txt.format(p.ADDR_WIDTH, + p.DATA_WIDTH, + p.PADDR_WIDTH))