X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fcompldst.py;h=0a0a4c2ee462613ad2f7974d688224a26463638c;hb=a7b8337867b15252dc1c63b7e3dc757d3449a6e1;hp=88d49647e41f74c4883a6e7b0b1fef1467d56582;hpb=cdfffd55cf53cd4a18ffadedb927129393abf089;p=soc.git

diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py
index 88d49647..0a0a4c2e 100644
--- a/src/experiment/compldst.py
+++ b/src/experiment/compldst.py
@@ -78,8 +78,12 @@ class LDSTCompUnit(Elaboratable):
         self.sto_rel_o = Signal(reset_less=True) # request store (to mem)
         self.req_rel_o = Signal(reset_less=True) # request write (result)
         self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
+
+        # hmm... TODO... move these to outside of LDSTCompUnit
         self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
         self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
+        self.ld_o = Signal(reset_less=True) # operation is a LD
+        self.st_o = Signal(reset_less=True) # operation is a ST
 
     def elaborate(self, platform):
         m = Module()
@@ -149,28 +153,28 @@ class LDSTCompUnit(Elaboratable):
         busy_o = self.busy_o
         comb += self.busy_o.eq(opc_l.q) # busy out
         comb += self.rd_rel_o.eq(src_l.q & busy_o) # src1/src2 req rel
-        comb += self.sto_rel_o.eq(sto_l.q & busy_o & self.shadown_i)
-
-        # address release only happens on LD/ST, and is shadowed.
-        comb += self.adr_rel_o.eq(adr_l.q & op_ldst & busy_o & self.shadown_i)
+        comb += self.sto_rel_o.eq(sto_l.q & busy_o & self.shadown_i & op_is_st)
 
         # request release enabled based on if op is a LD/ST or a plain ALU
-        # if op is a LD/ST, req_rel activates from the *address* latch
-        # if op is ADD/SUB, req_rel activates from the *dest* latch
+        # if op is an ADD/SUB or a LD, req_rel activates.
         wr_q = Signal(reset_less=True)
-        comb += wr_q.eq(Mux(op_ldst, adr_l.q, req_l.q))
-
-        # the counter is just for demo purposes, to get the ALUs of different
-        # types to take arbitrary completion times
-        with m.If(opc_l.qn):
-            sync += self.counter.eq(0) # reset counter when not busy
-        with m.If(req_l.qn & busy_o & (self.counter == 0)):
-            sync += self.counter.eq(2) # take 2 (fake) cycles to respond
-        with m.If(self.counter > 1):
-            sync += self.counter.eq(self.counter - 1)
-        with m.If(self.counter == 1):
+        comb += wr_q.eq(req_l.q & (~op_ldst | op_is_ld))
+
+        alulatch = Signal(reset_less=True)
+        comb += alulatch.eq((op_ldst & self.adr_rel_o) | \
+                            (~op_ldst & self.req_rel_o))
+
+        # only proceed if ALU says its output is valid
+        with m.If(self.alu.n_valid_o):
+
             # write req release out.  waits until shadow is dropped.
             comb += self.req_rel_o.eq(wr_q & busy_o & self.shadown_i)
+            # address release only happens on LD/ST, and is shadowed.
+            comb += self.adr_rel_o.eq(adr_l.q & op_ldst & busy_o & \
+                                      self.shadown_i)
+            # when output latch is ready, and ALU says ready, accept ALU output
+            with m.If(self.req_rel_o):
+                m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
 
         # select immediate if opcode says so.  however also change the latch
         # to trigger *from* the opcode latch instead.
@@ -189,7 +193,7 @@ class LDSTCompUnit(Elaboratable):
 
         # and one for the output from the ALU
         data_r = Signal(self.rwid, reset_less=True) # Dest register
-        latchregister(m, self.alu.o, data_r, req_l.q)
+        latchregister(m, self.alu.o, data_r, alulatch)
 
         # decode bits of operand (latched)
         comb += op_alu.eq(oper_r[0])
@@ -199,9 +203,18 @@ class LDSTCompUnit(Elaboratable):
         comb += op_ldst.eq(op_is_ld | op_is_st)
         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
-
-        with m.If(self.go_wr_i):
-            comb += self.data_o.eq(data_r)
+        comb += self.ld_o.eq(op_is_ld)
+        comb += self.st_o.eq(op_is_st)
+
+        # on a go_read, tell the ALU we're accepting data.
+        # NOTE: this spells TROUBLE if the ALU isn't ready!
+        # go_read is only valid for one clock!
+        with m.If(self.go_rd_i):                     # src operands ready, GO!
+            with m.If(~self.alu.p_ready_o):          # no ACK yet
+                m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
+
+        # put the register directly onto the output
+        comb += self.data_o.eq(data_r)
 
         return m