X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fscore6600.py;h=05de08fa1de491d280b0c635a54b705024396a6a;hb=a7b8337867b15252dc1c63b7e3dc757d3449a6e1;hp=e8b1e8bbbde7a9e060100193dfeb12d2f42c7b75;hpb=ab0309b710a191b1a8e3051a59b5ab298e75d601;p=soc.git

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index e8b1e8bb..05de08fa 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -121,6 +121,8 @@ class CompUnitsBase(Elaboratable):
         self.rd_rel_o = Signal(n_units, reset_less=True)
         self.req_rel_o = Signal(n_units, reset_less=True)
         if ldstmode:
+            self.ld_o = Signal(n_units, reset_less=True) # op is LD
+            self.st_o = Signal(n_units, reset_less=True) # op is ST
             self.adr_rel_o = Signal(n_units, reset_less=True)
             self.sto_rel_o = Signal(n_units, reset_less=True)
             self.req_rel_o = Signal(n_units, reset_less=True)
@@ -185,9 +187,13 @@ class CompUnitsBase(Elaboratable):
         stmem_l = []
         go_ad_l = []
         go_st_l = []
+        ld_l = []
+        st_l = []
         adr_rel_l = []
         sto_rel_l = []
         for alu in self.units:
+            ld_l.append(alu.ld_o)
+            st_l.append(alu.st_o)
             adr_rel_l.append(alu.adr_rel_o)
             sto_rel_l.append(alu.sto_rel_o)
             ldmem_l.append(alu.load_mem_o)
@@ -542,13 +548,25 @@ class Scoreboard(Elaboratable):
         #---------
         reset_b = Signal(cul.n_units, reset_less=True)
         sync += reset_b.eq(cul.go_st_i | cul.go_wr_i | cul.go_die_i)
+
+
         comb += memfus.fn_issue_i.eq(cul.issue_i) # Comp Unit Issue -> Mem FUs
         comb += memfus.addr_en_i.eq(cul.adr_rel_o) # Match enable on adr rel
         comb += memfus.addr_rs_i.eq(reset_b) # reset same as LDSTCompUnit
+
+        # LD/STs have to accumulate prior LD/STs (TODO: multi-issue as well,
+        # in a transitive fashion).  This cycle activates based on LDSTCompUnit
+        # issue_i.  multi-issue gets a bit more complex but not a lot.
+        prior_ldsts = Signal(cul.n_units, reset_less=True)
+        sync += prior_ldsts.eq(memfus.g_int_ld_pend_o | memfus.g_int_st_pend_o)
         with m.If(self.ls_oper_i[2]): # LD bit of operand
-            comb += memfus.ld_i.eq(cul.issue_i)
+            comb += memfus.ld_i.eq(cul.issue_i | prior_ldsts)
         with m.If(self.ls_oper_i[3]): # ST bit of operand
-            comb += memfus.st_i.eq(cul.issue_i)
+            comb += memfus.st_i.eq(cul.issue_i | prior_ldsts)
+
+        # TODO: adr_rel_o needs to go into L1 Cache.  for now,
+        # just immediately activate go_adr
+        comb += cul.go_ad_i.eq(cul.adr_rel_o)
 
         # connect up address data
         comb += memfus.addrs_i[0].eq(cul.units[0].data_o)
@@ -556,11 +574,16 @@ class Scoreboard(Elaboratable):
 
         # connect loadable / storable to go_ld/go_st.
         # XXX should only be done when the memory ld/st has actually happened!
-
-        comb += memfus.go_ld_i.eq(memfus.loadable_o & memfus.addr_nomatch_o)
-        comb += memfus.go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o)
+        go_st_i = Signal(cul.n_units, reset_less=True)
+        go_ld_i = Signal(cul.n_units, reset_less=True)
+        comb += go_ld_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\
+                                  cul.req_rel_o & cul.ld_o)
+        comb += go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\
+                                  cul.sto_rel_o & cul.st_o)
+        comb += memfus.go_ld_i.eq(go_ld_i)
+        comb += memfus.go_st_i.eq(go_st_i)
         #comb += cul.go_wr_i.eq(memfus.loadable_o & memfus.addr_nomatch_o)
-        comb += cul.go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o)
+        comb += cul.go_st_i.eq(go_st_i)
 
         #comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus])
         #comb += cu.go_wr_i[0:n_intfus].eq(go_wr_o[0:n_intfus])
@@ -620,7 +643,6 @@ class Scoreboard(Elaboratable):
         # ok connect first n_int_fu shadows to busy lines, to create an
         # instruction-order linked-list-like arrangement, using a bit-matrix
         # (instead of e.g. a ring buffer).
-        # XXX TODO
 
         # when written, the shadow can be cancelled (and was good)
         for i in range(n_intfus):
@@ -1128,7 +1150,7 @@ def scoreboard_sim(dut, alusim):
 
         if True: # LD/ST test (with immediate)
             instrs.append( (1, 2, 2, 0x10, 1, 1, (0, 0)) )
-            #instrs.append( (1, 2, 7, 0x10, 1, 1, (0, 0)) )
+            instrs.append( (1, 2, 7, 0x12, 1, 1, (0, 0)) )
 
         if False:
             instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )