X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fscore6600.py;h=0d9f897472a7510e90cdf76ea73794fbbcca1766;hb=1f9ca534b34a1206b11a895dbfbc327cbb7f8ff4;hp=602be44ed86e316b5654ce55596c64d08081088b;hpb=1f92c6f569be4ff53323c6b255191aad89e58a35;p=soc.git

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 602be44e..0d9f8974 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -181,6 +181,7 @@ class CompUnitALUs(CompUnitsBase):
 
         # inputs
         self.oper_i = Signal(opwid, reset_less=True)
+        self.imm_i = Signal(rwid, reset_less=True)
 
         # Int ALUs
         add = ALU(rwid)
@@ -190,7 +191,8 @@ class CompUnitALUs(CompUnitsBase):
 
         units = []
         for alu in [add, sub, mul, shf]:
-            units.append(ComputationUnitNoDelay(rwid, 2, alu))
+            aluopwid = 3 # extra bit for immediate mode
+            units.append(ComputationUnitNoDelay(rwid, aluopwid, alu))
 
         CompUnitsBase.__init__(self, rwid, units)
 
@@ -198,13 +200,10 @@ class CompUnitALUs(CompUnitsBase):
         m = CompUnitsBase.elaborate(self, platform)
         comb = m.d.comb
 
-        # hand the same operation to all units
+        # hand the same operation to all units, only lower 2 bits though
         for alu in self.units:
-            comb += alu.oper_i.eq(self.oper_i)
-        #comb += self.units[0].oper_i.eq(Const(0, 2)) # op=add
-        #comb += self.units[1].oper_i.eq(Const(1, 2)) # op=sub
-        #comb += self.units[2].oper_i.eq(Const(2, 2)) # op=mul
-        #comb += self.units[3].oper_i.eq(Const(3, 2)) # op=shf
+            comb += alu.oper_i[0:3].eq(self.oper_i)
+            comb += alu.imm_i.eq(self.imm_i)
 
         return m
 
@@ -237,7 +236,6 @@ class CompUnitBR(CompUnitsBase):
         # hand the same operation to all units
         for alu in self.units:
             comb += alu.oper_i.eq(self.oper_i)
-        #comb += self.br1.oper_i.eq(Const(4, 3)) # op=bgt
 
         return m
 
@@ -338,6 +336,7 @@ class Scoreboard(Elaboratable):
         self.brissue = IssueUnitGroup(1)
         # and these
         self.alu_oper_i = Signal(4, reset_less=True)
+        self.alu_imm_i = Signal(rwid, reset_less=True)
         self.br_oper_i = Signal(4, reset_less=True)
 
         # inputs
@@ -377,7 +376,7 @@ class Scoreboard(Elaboratable):
 
         # Int ALUs and Comp Units
         n_int_alus = 5
-        cua = CompUnitALUs(self.rwid, 2)
+        cua = CompUnitALUs(self.rwid, 3)
         cub = CompUnitBR(self.rwid, 2)
         m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub])
         bgt = cub.bgt # get at the branch computation unit
@@ -432,6 +431,7 @@ class Scoreboard(Elaboratable):
 
         # take these to outside (issue needs them)
         comb += cua.oper_i.eq(self.alu_oper_i)
+        comb += cua.imm_i.eq(self.alu_imm_i)
         comb += cub.oper_i.eq(self.br_oper_i)
 
         # TODO: issueunit.f (FP)
@@ -654,10 +654,12 @@ class IssueToScoreboard(Elaboratable):
         # "resetting" done above (insn_i=0) could be re-ASSERTed.
         with m.If(iq.qlen_o != 0):
             # get the operands and operation
+            imm = iq.data_o[0].imm_i
             dest = iq.data_o[0].dest_i
             src1 = iq.data_o[0].src1_i
             src2 = iq.data_o[0].src2_i
             op = iq.data_o[0].oper_i
+            opi = iq.data_o[0].opim_i # immediate set
 
             # set the src/dest regs
             comb += sc.int_dest_i.eq(dest)
@@ -672,7 +674,8 @@ class IssueToScoreboard(Elaboratable):
                 comb += wait_issue_br.eq(1)
             with m.Else():                   # alu
                 comb += sc.aluissue.insn_i.eq(1)
-                comb += sc.alu_oper_i.eq(op & 0x3)
+                comb += sc.alu_oper_i.eq(Cat(op[0:2], opi))
+                comb += sc.alu_imm_i.eq(imm)
                 comb += wait_issue_alu.eq(1)
 
             # XXX TODO
@@ -708,10 +711,12 @@ class RegSim:
         self.rwidth = rwidth
         self.regs = [0] * nregs
 
-    def op(self, op, op_imm, src1, src2, dest):
+    def op(self, op, op_imm, imm, src1, src2, dest):
         maxbits = (1 << self.rwidth) - 1
         src1 = self.regs[src1] & maxbits
-        if not op_imm: # put op in src2
+        if op_imm:
+            src2 = imm
+        else:
             src2 = self.regs[src2] & maxbits
         if op == IADD:
             val = src1 + src2
@@ -751,8 +756,9 @@ class RegSim:
                 yield from self.dump(dut)
                 assert False
 
-def instr_q(dut, op, op_imm, src1, src2, dest, branch_success, branch_fail):
-    instrs = [{'oper_i': op, 'dest_i': dest, 'opim_i': op_imm,
+def instr_q(dut, op, op_imm, imm, src1, src2, dest,
+            branch_success, branch_fail):
+    instrs = [{'oper_i': op, 'dest_i': dest, 'imm_i': imm, 'opim_i': op_imm,
                'src1_i': src1, 'src2_i': src2}]
 
     sendlen = 1
@@ -770,7 +776,7 @@ def instr_q(dut, op, op_imm, src1, src2, dest, branch_success, branch_fail):
     yield dut.p_add_i.eq(0)
 
 
-def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail):
+def int_instr(dut, op, imm, src1, src2, dest, branch_success, branch_fail):
     yield from disable_issue(dut)
     yield dut.int_dest_i.eq(dest)
     yield dut.int_src1_i.eq(src1)
@@ -782,6 +788,7 @@ def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail):
     else:
         yield dut.aluissue.insn_i.eq(1)
         yield dut.alu_oper_i.eq(Const(op & 0x3, 2))
+        yield dut.alu_imm_i.eq(imm)
         dut_issue = dut.aluissue
     yield dut.reg_enable_i.eq(1)
 
@@ -808,14 +815,15 @@ def create_random_ops(dut, n_ops, shadowing=False, max_opnums=3):
     for i in range(n_ops):
         src1 = randint(1, dut.n_regs-1)
         src2 = randint(1, dut.n_regs-1)
+        imm = randint(1, (1<<dut.rwid)-1)
         dest = randint(1, dut.n_regs-1)
         op = randint(0, max_opnums)
-        opi = 0 # if randint(0, 3) else 1 # set true if random is nonzero
+        opi = 0 if randint(0, 3) else 1 # set true if random is nonzero
 
         if shadowing:
-            insts.append((src1, src2, dest, op, opi, (0, 0)))
+            insts.append((src1, src2, dest, op, opi, imm, (0, 0)))
         else:
-            insts.append((src1, src2, dest, op, opi))
+            insts.append((src1, src2, dest, op, opi, imm))
     return insts
 
 
@@ -974,9 +982,12 @@ def scoreboard_sim(dut, alusim):
 
         # create some instructions (some random, some regression tests)
         instrs = []
-        if True:
+        if False:
             instrs = create_random_ops(dut, 15, True, 3)
 
+        if True:
+            instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )
+
         if False:
             instrs.append( (7, 3, 2, 4, (0, 0)) )
             instrs.append( (7, 6, 6, 2, (0, 0)) )
@@ -1070,11 +1081,13 @@ def scoreboard_sim(dut, alusim):
 
         # issue instruction(s), wait for issue to be free before proceeding
         for i, instr in enumerate(instrs):
-            src1, src2, dest, op, opi, (br_ok, br_fail) = instr
+            src1, src2, dest, op, opi, imm, (br_ok, br_fail) = instr
 
-            print ("instr %d: (%d, %d, %d, %d)" % (i, src1, src2, dest, op))
-            alusim.op(op, opi, src1, src2, dest)
-            yield from instr_q(dut, op, opi, src1, src2, dest, br_ok, br_fail)
+            print ("instr %d: (%d, %d, %d, %d, %d, %d)" % \
+                    (i, src1, src2, dest, op, opi, imm))
+            alusim.op(op, opi, imm, src1, src2, dest)
+            yield from instr_q(dut, op, opi, imm, src1, src2, dest,
+                               br_ok, br_fail)
 
         # wait for all instructions to stop before checking
         while True: