X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fscore6600.py;h=12d4d625f7f0feb4cde64b5a25da88cc84cc72bd;hb=ba68e8c70ded11443bc0cbc407b7aa1993dbc641;hp=b265bf976c1e6d7fc184df6865959000f7857c2d;hpb=d81c8deca026671d6472a92e3b5e2004d53892f1;p=soc.git diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index b265bf97..12d4d625 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -3,63 +3,92 @@ from nmigen.cli import verilog, rtlil from nmigen import Module, Const, Signal, Array, Cat, Elaboratable from regfile.regfile import RegFileArray, treereduce -from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit from scoreboard.fu_fu_matrix import FUFUDepMatrix from scoreboard.fu_reg_matrix import FURegDepMatrix from scoreboard.global_pending import GlobalPending from scoreboard.group_picker import GroupPicker -from scoreboard.issue_unit import IntFPIssueUnit, RegDecode -from scoreboard.shadow import ShadowMatrix, WaWGrid +from scoreboard.issue_unit import IssueUnitGroup, IssueUnitArray, RegDecode +from scoreboard.shadow import ShadowMatrix, BranchSpeculationRecord +from scoreboard.instruction_q import Instruction, InstructionQ from compalu import ComputationUnitNoDelay -from alu_hier import ALU +from alu_hier import ALU, BranchALU from nmutil.latch import SRLatch - -from random import randint - -class CompUnits(Elaboratable): - - def __init__(self, rwid, n_units): +from nmutil.nmoperator import eq + +from random import randint, seed +from copy import deepcopy +from math import log + + +class CompUnitsBase(Elaboratable): + """ Computation Unit Base class. + + Amazingly, this class works recursively. It's supposed to just + look after some ALUs (that can handle the same operations), + grouping them together, however it turns out that the same code + can also group *groups* of Computation Units together as well. + + Basically it was intended just to concatenate the ALU's issue, + go_rd etc. signals together, which start out as bits and become + sequences. Turns out that the same trick works just as well + on Computation Units! + + So this class may be used recursively to present a top-level + sequential concatenation of all the signals in and out of + ALUs, whilst at the same time making it convenient to group + ALUs together. + + At the lower level, the intent is that groups of (identical) + ALUs may be passed the same operation. Even beyond that, + the intent is that that group of (identical) ALUs actually + share the *same pipeline* and as such become a "Concurrent + Computation Unit" as defined by Mitch Alsup (see section + 11.4.9.3) + """ + def __init__(self, rwid, units): """ Inputs: * :rwid: bit width of register file(s) - both FP and INT - * :n_units: number of ALUs + * :units: sequence of ALUs (or CompUnitsBase derivatives) """ - self.n_units = n_units + self.units = units self.rwid = rwid + self.rwid = rwid + if units and isinstance(units[0], CompUnitsBase): + self.n_units = 0 + for u in self.units: + self.n_units += u.n_units + else: + self.n_units = len(units) + + n_units = self.n_units + # inputs self.issue_i = Signal(n_units, reset_less=True) self.go_rd_i = Signal(n_units, reset_less=True) self.go_wr_i = Signal(n_units, reset_less=True) self.shadown_i = Signal(n_units, reset_less=True) self.go_die_i = Signal(n_units, reset_less=True) + + # outputs self.busy_o = Signal(n_units, reset_less=True) self.rd_rel_o = Signal(n_units, reset_less=True) self.req_rel_o = Signal(n_units, reset_less=True) - self.dest_o = Signal(rwid, reset_less=True) - self.src1_data_i = Signal(rwid, reset_less=True) - self.src2_data_i = Signal(rwid, reset_less=True) + # in/out register data (note: not register#, actual data) + self.data_o = Signal(rwid, reset_less=True) + self.src1_i = Signal(rwid, reset_less=True) + self.src2_i = Signal(rwid, reset_less=True) + # input operand def elaborate(self, platform): m = Module() + comb = m.d.comb - # Int ALUs - add = ALU(self.rwid) - sub = ALU(self.rwid) - mul = ALU(self.rwid) - shf = ALU(self.rwid) - m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 2, add) - m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 2, sub) - m.submodules.comp3 = comp3 = ComputationUnitNoDelay(self.rwid, 2, mul) - m.submodules.comp4 = comp4 = ComputationUnitNoDelay(self.rwid, 2, shf) - int_alus = [comp1, comp2, comp3, comp4] - - m.d.comb += comp1.oper_i.eq(Const(0, 2)) # op=add - m.d.comb += comp2.oper_i.eq(Const(1, 2)) # op=sub - m.d.comb += comp3.oper_i.eq(Const(2, 2)) # op=mul - m.d.comb += comp4.oper_i.eq(Const(3, 2)) # op=shf + for i, alu in enumerate(self.units): + setattr(m.submodules, "comp%d" % i, alu) go_rd_l = [] go_wr_l = [] @@ -69,7 +98,7 @@ class CompUnits(Elaboratable): rd_rel_l = [] shadow_l = [] godie_l = [] - for alu in int_alus: + for alu in self.units: req_rel_l.append(alu.req_rel_o) rd_rel_l.append(alu.rd_rel_o) shadow_l.append(alu.shadown_i) @@ -78,25 +107,99 @@ class CompUnits(Elaboratable): go_rd_l.append(alu.go_rd_i) issue_l.append(alu.issue_i) busy_l.append(alu.busy_o) - m.d.comb += self.rd_rel_o.eq(Cat(*rd_rel_l)) - m.d.comb += self.req_rel_o.eq(Cat(*req_rel_l)) - m.d.comb += self.busy_o.eq(Cat(*busy_l)) - m.d.comb += Cat(*godie_l).eq(self.go_die_i) - m.d.comb += Cat(*shadow_l).eq(self.shadown_i) - m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i) - m.d.comb += Cat(*go_rd_l).eq(self.go_rd_i) - m.d.comb += Cat(*issue_l).eq(self.issue_i) + comb += self.rd_rel_o.eq(Cat(*rd_rel_l)) + comb += self.req_rel_o.eq(Cat(*req_rel_l)) + comb += self.busy_o.eq(Cat(*busy_l)) + comb += Cat(*godie_l).eq(self.go_die_i) + comb += Cat(*shadow_l).eq(self.shadown_i) + comb += Cat(*go_wr_l).eq(self.go_wr_i) + comb += Cat(*go_rd_l).eq(self.go_rd_i) + comb += Cat(*issue_l).eq(self.issue_i) # connect data register input/output # merge (OR) all integer FU / ALU outputs to a single value - # bit of a hack: treereduce needs a list with an item named "dest_o" - dest_o = treereduce(int_alus) - m.d.comb += self.dest_o.eq(dest_o) + # bit of a hack: treereduce needs a list with an item named "data_o" + if self.units: + data_o = treereduce(self.units) + comb += self.data_o.eq(data_o) + + for i, alu in enumerate(self.units): + comb += alu.src1_i.eq(self.src1_i) + comb += alu.src2_i.eq(self.src2_i) + + return m + + +class CompUnitALUs(CompUnitsBase): + + def __init__(self, rwid, opwid): + """ Inputs: + + * :rwid: bit width of register file(s) - both FP and INT + * :opwid: operand bit width + """ + self.opwid = opwid + + # inputs + self.oper_i = Signal(opwid, reset_less=True) + + # Int ALUs + add = ALU(rwid) + sub = ALU(rwid) + mul = ALU(rwid) + shf = ALU(rwid) + + units = [] + for alu in [add, sub, mul, shf]: + units.append(ComputationUnitNoDelay(rwid, 2, alu)) + + CompUnitsBase.__init__(self, rwid, units) + + def elaborate(self, platform): + m = CompUnitsBase.elaborate(self, platform) + comb = m.d.comb + + # hand the same operation to all units + for alu in self.units: + comb += alu.oper_i.eq(self.oper_i) + #comb += self.units[0].oper_i.eq(Const(0, 2)) # op=add + #comb += self.units[1].oper_i.eq(Const(1, 2)) # op=sub + #comb += self.units[2].oper_i.eq(Const(2, 2)) # op=mul + #comb += self.units[3].oper_i.eq(Const(3, 2)) # op=shf + + return m + + +class CompUnitBR(CompUnitsBase): + + def __init__(self, rwid, opwid): + """ Inputs: + + * :rwid: bit width of register file(s) - both FP and INT + * :opwid: operand bit width + + Note: bgt unit is returned so that a shadow unit can be created + for it + """ + self.opwid = opwid + + # inputs + self.oper_i = Signal(opwid, reset_less=True) - for i, alu in enumerate(int_alus): - m.d.comb += alu.src1_i.eq(self.src1_data_i) - m.d.comb += alu.src2_i.eq(self.src2_data_i) + # Branch ALU and CU + self.bgt = BranchALU(rwid) + self.br1 = ComputationUnitNoDelay(rwid, 3, self.bgt) + CompUnitsBase.__init__(self, rwid, [self.br1]) + + def elaborate(self, platform): + m = CompUnitsBase.elaborate(self, platform) + comb = m.d.comb + + # hand the same operation to all units + for alu in self.units: + comb += alu.oper_i.eq(self.oper_i) + #comb += self.br1.oper_i.eq(Const(4, 3)) # op=bgt return m @@ -124,6 +227,7 @@ class FunctionUnits(Elaboratable): self.go_rd_i = Signal(n_int_alus, reset_less=True) self.go_wr_i = Signal(n_int_alus, reset_less=True) + self.go_die_i = Signal(n_int_alus, reset_less=True) self.req_rel_o = Signal(n_int_alus, reset_less=True) self.fn_issue_i = Signal(n_int_alus, reset_less=True) @@ -131,44 +235,48 @@ class FunctionUnits(Elaboratable): def elaborate(self, platform): m = Module() + comb = m.d.comb + sync = m.d.sync - n_int_fus = self.n_int_alus + n_intfus = self.n_int_alus # Integer FU-FU Dep Matrix - intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus) + intfudeps = FUFUDepMatrix(n_intfus, n_intfus) m.submodules.intfudeps = intfudeps # Integer FU-Reg Dep Matrix - intregdeps = FURegDepMatrix(n_int_fus, self.n_regs) + intregdeps = FURegDepMatrix(n_intfus, self.n_regs) m.submodules.intregdeps = intregdeps - m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o) - m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o) + comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o) + comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o) - m.d.comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o) - m.d.comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o) + comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o) + comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o) - m.d.comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o) - m.d.comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o) + comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o) + comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o) self.wr_pend_o = intregdeps.wr_pend_o # also output for use in WaWGrid - m.d.comb += intfudeps.issue_i.eq(self.fn_issue_i) - m.d.comb += intfudeps.go_rd_i.eq(self.go_rd_i) - m.d.comb += intfudeps.go_wr_i.eq(self.go_wr_i) - m.d.comb += self.readable_o.eq(intfudeps.readable_o) - m.d.comb += self.writable_o.eq(intfudeps.writable_o) + comb += intfudeps.issue_i.eq(self.fn_issue_i) + comb += intfudeps.go_rd_i.eq(self.go_rd_i) + comb += intfudeps.go_wr_i.eq(self.go_wr_i) + comb += intfudeps.go_die_i.eq(self.go_die_i) + comb += self.readable_o.eq(intfudeps.readable_o) + comb += self.writable_o.eq(intfudeps.writable_o) # Connect function issue / arrays, and dest/src1/src2 - m.d.comb += intregdeps.dest_i.eq(self.dest_i) - m.d.comb += intregdeps.src1_i.eq(self.src1_i) - m.d.comb += intregdeps.src2_i.eq(self.src2_i) + comb += intregdeps.dest_i.eq(self.dest_i) + comb += intregdeps.src1_i.eq(self.src1_i) + comb += intregdeps.src2_i.eq(self.src2_i) - m.d.comb += intregdeps.go_rd_i.eq(self.go_rd_i) - m.d.comb += intregdeps.go_wr_i.eq(self.go_wr_i) - m.d.comb += intregdeps.issue_i.eq(self.fn_issue_i) + comb += intregdeps.go_rd_i.eq(self.go_rd_i) + comb += intregdeps.go_wr_i.eq(self.go_wr_i) + comb += intregdeps.go_die_i.eq(self.go_die_i) + comb += intregdeps.issue_i.eq(self.fn_issue_i) - m.d.comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o) - m.d.comb += self.src1_rsel_o.eq(intregdeps.src1_rsel_o) - m.d.comb += self.src2_rsel_o.eq(intregdeps.src2_rsel_o) + comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o) + comb += self.src1_rsel_o.eq(intregdeps.src1_rsel_o) + comb += self.src2_rsel_o.eq(intregdeps.src2_rsel_o) return m @@ -187,18 +295,35 @@ class Scoreboard(Elaboratable): self.intregs = RegFileArray(rwid, n_regs) self.fpregs = RegFileArray(rwid, n_regs) + # issue q needs to get at these + self.aluissue = IssueUnitGroup(4) + self.brissue = IssueUnitGroup(1) + # and these + self.alu_oper_i = Signal(4, reset_less=True) + self.br_oper_i = Signal(4, reset_less=True) + # inputs - self.int_store_i = Signal(reset_less=True) # instruction is a store self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in self.reg_enable_i = Signal(reset_less=True) # enable reg decode + # outputs self.issue_o = Signal(reset_less=True) # instruction was accepted self.busy_o = Signal(reset_less=True) # at least one CU is busy + # for branch speculation experiment. branch_direction = 0 if + # the branch hasn't been met yet. 1 indicates "success", 2 is "fail" + # branch_succ and branch_fail are requests to have the current + # instruction be dependent on the branch unit "shadow" capability. + self.branch_succ_i = Signal(reset_less=True) + self.branch_fail_i = Signal(reset_less=True) + self.branch_direction_o = Signal(2, reset_less=True) + def elaborate(self, platform): m = Module() + comb = m.d.comb + sync = m.d.sync m.submodules.intregs = self.intregs m.submodules.fpregs = self.fpregs @@ -213,40 +338,44 @@ class Scoreboard(Elaboratable): fp_src2 = self.fpregs.read_port("src2") # Int ALUs and Comp Units - n_int_alus = 4 - m.submodules.cu = cu = CompUnits(self.rwid, n_int_alus) - m.d.comb += cu.shadown_i.eq(-1) - m.d.comb += cu.go_die_i.eq(0) + n_int_alus = 5 + cua = CompUnitALUs(self.rwid, 2) + cub = CompUnitBR(self.rwid, 2) + m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub]) + bgt = cub.bgt # get at the branch computation unit + br1 = cub.br1 # Int FUs m.submodules.intfus = intfus = FunctionUnits(self.n_regs, n_int_alus) # Count of number of FUs - n_int_fus = n_int_alus + n_intfus = n_int_alus n_fp_fus = 0 # for now # Integer Priority Picker 1: Adder + Subtractor - intpick1 = GroupPicker(n_int_fus) # picks between add, sub, mul and shf + intpick1 = GroupPicker(n_intfus) # picks between add, sub, mul and shf m.submodules.intpick1 = intpick1 # INT/FP Issue Unit regdecode = RegDecode(self.n_regs) m.submodules.regdecode = regdecode - issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus) + issueunit = IssueUnitArray([self.aluissue, self.brissue]) m.submodules.issueunit = issueunit - # Shadow Matrix. currently n_int_fus shadows, to be used for - # write-after-write hazards - m.submodules.shadows = shadows = ShadowMatrix(n_int_fus, n_int_fus) - go_rd_rst = Signal(n_int_fus, reset_less=True) - go_wr_rst = Signal(n_int_fus, reset_less=True) + # Shadow Matrix. currently n_intfus shadows, to be used for + # write-after-write hazards. NOTE: there is one extra for branches, + # so the shadow width is increased by 1 + m.submodules.shadows = shadows = ShadowMatrix(n_intfus, n_intfus, True) + m.submodules.bshadow = bshadow = ShadowMatrix(n_intfus, 1, False) + + # record previous instruction to cast shadow on current instruction + fn_issue_prev = Signal(n_intfus) + prev_shadow = Signal(n_intfus) - # Write-after-Write grid: selects one shadow to enable, based - # on which unit(s) have writes pending and the current instruction - # also needing to write - m.submodules.wawgrid = wawgrid = WaWGrid(n_int_fus, n_int_fus) - busy_prev = Signal(n_int_fus) - busy_curr = Signal(n_int_fus) + # Branch Speculation recorder. tracks the success/fail state as + # each instruction is issued, so that when the branch occurs the + # allow/cancel can be issued as appropriate. + m.submodules.specrec = bspec = BranchSpeculationRecord(n_intfus) #--------- # ok start wiring things together... @@ -257,30 +386,42 @@ class Scoreboard(Elaboratable): #--------- # Issue Unit is where it starts. set up some in/outs for this module #--------- - m.d.comb += [issueunit.i.store_i.eq(self.int_store_i), - regdecode.dest_i.eq(self.int_dest_i), + comb += [ regdecode.dest_i.eq(self.int_dest_i), regdecode.src1_i.eq(self.int_src1_i), regdecode.src2_i.eq(self.int_src2_i), regdecode.enable_i.eq(self.reg_enable_i), - issueunit.i.dest_i.eq(regdecode.dest_o), self.issue_o.eq(issueunit.issue_o) ] - self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode - # connect global rd/wr pending vector (for WaW detection) - m.d.sync += issueunit.i.g_wr_pend_i.eq(intfus.g_int_wr_pend_o) + # take these to outside (issue needs them) + comb += cua.oper_i.eq(self.alu_oper_i) + comb += cub.oper_i.eq(self.br_oper_i) + # TODO: issueunit.f (FP) # and int function issue / busy arrays, and dest/src1/src2 - m.d.comb += intfus.dest_i.eq(regdecode.dest_o) - m.d.comb += intfus.src1_i.eq(regdecode.src1_o) - m.d.comb += intfus.src2_i.eq(regdecode.src2_o) + comb += intfus.dest_i.eq(regdecode.dest_o) + comb += intfus.src1_i.eq(regdecode.src1_o) + comb += intfus.src2_i.eq(regdecode.src2_o) - fn_issue_o = issueunit.i.fn_issue_o + fn_issue_o = issueunit.fn_issue_o - m.d.comb += intfus.fn_issue_i.eq(fn_issue_o) - m.d.comb += issueunit.i.busy_i.eq(cu.busy_o) - m.d.comb += self.busy_o.eq(cu.busy_o.bool()) + comb += intfus.fn_issue_i.eq(fn_issue_o) + comb += issueunit.busy_i.eq(cu.busy_o) + comb += self.busy_o.eq(cu.busy_o.bool()) + + #--------- + # merge shadow matrices outputs + #--------- + + # these are explained in ShadowMatrix docstring, and are to be + # connected to the FUReg and FUFU Matrices, to get them to reset + anydie = Signal(n_intfus, reset_less=True) + allshadown = Signal(n_intfus, reset_less=True) + shreset = Signal(n_intfus, reset_less=True) + comb += allshadown.eq(shadows.shadown_o & bshadow.shadown_o) + comb += anydie.eq(shadows.go_die_o | bshadow.go_die_o) + comb += shreset.eq(bspec.match_g_o | bspec.match_f_o) #--------- # connect fu-fu matrix @@ -291,34 +432,34 @@ class Scoreboard(Elaboratable): go_wr_o = intpick1.go_wr_o go_rd_i = intfus.go_rd_i go_wr_i = intfus.go_wr_i + go_die_i = intfus.go_die_i # NOTE: connect to the shadowed versions so that they can "die" (reset) - m.d.comb += go_rd_i[0:n_int_fus].eq(go_rd_rst[0:n_int_fus]) # rd - m.d.comb += go_wr_i[0:n_int_fus].eq(go_wr_rst[0:n_int_fus]) # wr + comb += go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus]) # rd + comb += go_wr_i[0:n_intfus].eq(go_wr_o[0:n_intfus]) # wr + comb += go_die_i[0:n_intfus].eq(anydie[0:n_intfus]) # die # Connect Picker #--------- - m.d.comb += intpick1.rd_rel_i[0:n_int_fus].eq(cu.rd_rel_o[0:n_int_fus]) - m.d.comb += intpick1.req_rel_i[0:n_int_fus].eq(cu.req_rel_o[0:n_int_fus]) + comb += intpick1.rd_rel_i[0:n_intfus].eq(cu.rd_rel_o[0:n_intfus]) + comb += intpick1.req_rel_i[0:n_intfus].eq(cu.req_rel_o[0:n_intfus]) int_rd_o = intfus.readable_o int_wr_o = intfus.writable_o - m.d.comb += intpick1.readable_i[0:n_int_fus].eq(int_rd_o[0:n_int_fus]) - m.d.comb += intpick1.writable_i[0:n_int_fus].eq(int_wr_o[0:n_int_fus]) + comb += intpick1.readable_i[0:n_intfus].eq(int_rd_o[0:n_intfus]) + comb += intpick1.writable_i[0:n_intfus].eq(int_wr_o[0:n_intfus]) #--------- # Shadow Matrix #--------- - m.d.comb += shadows.issue_i.eq(fn_issue_o) - # these are explained in ShadowMatrix docstring, and are to be - # connected to the FUReg and FUFU Matrices, to get them to reset - # NOTE: do NOT connect these to the Computation Units. The CUs need to - # do something slightly different (due to the revolving-door SRLatches) - m.d.comb += go_rd_rst.eq(go_rd_o | shadows.go_die_o) - m.d.comb += go_wr_rst.eq(go_wr_o | shadows.go_die_o) + comb += shadows.issue_i.eq(fn_issue_o) + #comb += shadows.reset_i[0:n_intfus].eq(bshadow.go_die_o[0:n_intfus]) + comb += shadows.reset_i[0:n_intfus].eq(bshadow.go_die_o[0:n_intfus]) + #--------- + # NOTE; this setup is for the instruction order preservation... # connect shadows / go_dies to Computation Units - m.d.comb += cu.shadown_i[0:n_int_fus].eq(shadows.shadown_o[0:n_int_fus]) - m.d.comb += cu.go_die_i[0:n_int_fus].eq(shadows.go_die_o[0:n_int_fus]) + comb += cu.shadown_i[0:n_intfus].eq(allshadown) + comb += cu.go_die_i[0:n_intfus].eq(anydie) # ok connect first n_int_fu shadows to busy lines, to create an # instruction-order linked-list-like arrangement, using a bit-matrix @@ -326,49 +467,194 @@ class Scoreboard(Elaboratable): # XXX TODO # when written, the shadow can be cancelled (and was good) - m.d.comb += shadows.s_good_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus]) + for i in range(n_intfus): + comb += shadows.s_good_i[i][0:n_intfus].eq(go_wr_o[0:n_intfus]) # work out the current-activated busy unit (by recording the old one) - with m.If(self.issue_o): # only update busy_prev if instruction issued - m.d.sync += busy_prev.eq(cu.busy_o) - m.d.comb += busy_curr.eq(~busy_prev & cu.busy_o) + with m.If(fn_issue_o): # only update prev bit if instruction issued + sync += fn_issue_prev.eq(fn_issue_o) + + # *previous* instruction shadows *current* instruction, and, obviously, + # if the previous is completed (!busy) don't cast the shadow! + comb += prev_shadow.eq(~fn_issue_o & cu.busy_o) + for i in range(n_intfus): + comb += shadows.shadow_i[i][0:n_intfus].eq(prev_shadow) + + #--------- + # ... and this is for branch speculation. it uses the extra bit + # tacked onto the ShadowMatrix (hence shadow_wid=n_intfus+1) + # only needs to set shadow_i, s_fail_i and s_good_i + + # issue captures shadow_i (if enabled) + comb += bshadow.reset_i[0:n_intfus].eq(shreset[0:n_intfus]) + + bactive = Signal(reset_less=True) + comb += bactive.eq((bspec.active_i | br1.issue_i) & ~br1.go_wr_i) + + # instruction being issued (fn_issue_o) has a shadow cast by the branch + with m.If(bactive & (self.branch_succ_i | self.branch_fail_i)): + comb += bshadow.issue_i.eq(fn_issue_o) + for i in range(n_intfus): + with m.If(fn_issue_o & (Const(1<> (src2 & maxbits) + elif op == IBGT: + val = int(src1 > src2) + elif op == IBLT: + val = int(src1 < src2) + elif op == IBEQ: + val = int(src1 == src2) + elif op == IBNE: + val = int(src1 != src2) val &= maxbits - self.regs[dest] = val + self.setval(dest, val) + return val def setval(self, dest, val): + print ("sim setval", dest, hex(val)) self.regs[dest] = val def dump(self, dut): @@ -415,15 +715,46 @@ class RegSim: yield from self.dump(dut) assert False -def int_instr(dut, alusim, op, src1, src2, dest): - for i in range(len(dut.int_insn_i)): - yield dut.int_insn_i[i].eq(0) +def instr_q(dut, op, src1, src2, dest, branch_success, branch_fail): + instrs = [{'oper_i': op, 'dest_i': dest, 'src1_i': src1, 'src2_i': src2}] + + sendlen = 1 + for idx in range(sendlen): + yield from eq(dut.data_i[idx], instrs[idx]) + di = yield dut.data_i[idx] + print ("senddata %d %x" % (idx, di)) + yield dut.p_add_i.eq(sendlen) + yield + o_p_ready = yield dut.p_ready_o + while not o_p_ready: + yield + o_p_ready = yield dut.p_ready_o + + yield dut.p_add_i.eq(0) + + +def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail): + yield from disable_issue(dut) yield dut.int_dest_i.eq(dest) yield dut.int_src1_i.eq(src1) yield dut.int_src2_i.eq(src2) - yield dut.int_insn_i[op].eq(1) + if (op & (0x3<<2)) != 0: # branch + yield dut.brissue.insn_i.eq(1) + yield dut.br_oper_i.eq(Const(op & 0x3, 2)) + dut_issue = dut.brissue + else: + yield dut.aluissue.insn_i.eq(1) + yield dut.alu_oper_i.eq(Const(op & 0x3, 2)) + dut_issue = dut.aluissue yield dut.reg_enable_i.eq(1) - alusim.op(op, src1, src2, dest) + + # these indicate that the instruction is to be made shadow-dependent on + # (either) branch success or branch fail + yield dut.branch_fail_i.eq(branch_fail) + yield dut.branch_succ_i.eq(branch_success) + + yield + yield from wait_for_issue(dut, dut_issue) def print_reg(dut, rnums): @@ -435,12 +766,58 @@ def print_reg(dut, rnums): print ("reg %s: %s" % (','.join(rnums), ','.join(rs))) -def scoreboard_sim(dut, alusim): +def create_random_ops(dut, n_ops, shadowing=False, max_opnums=3): + insts = [] + for i in range(n_ops): + src1 = randint(1, dut.n_regs-1) + src2 = randint(1, dut.n_regs-1) + dest = randint(1, dut.n_regs-1) + op = randint(0, max_opnums) + + if shadowing: + insts.append((src1, src2, dest, op, (0, 0))) + else: + insts.append((src1, src2, dest, op)) + return insts + + +def wait_for_busy_clear(dut): + while True: + busy_o = yield dut.busy_o + if not busy_o: + break + print ("busy",) + yield + +def disable_issue(dut): + yield dut.aluissue.insn_i.eq(0) + yield dut.brissue.insn_i.eq(0) + - yield dut.int_store_i.eq(0) +def wait_for_issue(dut, dut_issue): + while True: + issue_o = yield dut_issue.fn_issue_o + if issue_o: + yield from disable_issue(dut) + yield dut.reg_enable_i.eq(0) + break + print ("busy",) + #yield from print_reg(dut, [1,2,3]) + yield + #yield from print_reg(dut, [1,2,3]) + +def scoreboard_branch_sim(dut, alusim): + + iseed = 3 for i in range(1): + print ("rseed", iseed) + seed(iseed) + iseed += 1 + + yield dut.branch_direction_o.eq(0) + # set random values in the registers for i in range(1, dut.n_regs): val = 31+i*3 @@ -448,30 +825,132 @@ def scoreboard_sim(dut, alusim): yield dut.intregs.regs[i].reg.eq(val) alusim.setval(i, val) + if False: + # create some instructions: branches create a tree + insts = create_random_ops(dut, 1, True, 1) + #insts.append((6, 6, 1, 2, (0, 0))) + #insts.append((4, 3, 3, 0, (0, 0))) + + src1 = randint(1, dut.n_regs-1) + src2 = randint(1, dut.n_regs-1) + #op = randint(4, 7) + op = 4 # only BGT at the moment + + branch_ok = create_random_ops(dut, 1, True, 1) + branch_fail = create_random_ops(dut, 1, True, 1) + + insts.append((src1, src2, (branch_ok, branch_fail), op, (0, 0))) + + if True: + insts = [] + insts.append( (3, 5, 2, 0, (0, 0)) ) + branch_ok = [] + branch_fail = [] + #branch_ok.append ( (5, 7, 5, 1, (1, 0)) ) + branch_ok.append( None ) + branch_fail.append( (1, 1, 2, 0, (0, 1)) ) + #branch_fail.append( None ) + insts.append( (6, 4, (branch_ok, branch_fail), 4, (0, 0)) ) + + siminsts = deepcopy(insts) + + # issue instruction(s) + i = -1 + instrs = insts + branch_direction = 0 + while instrs: + yield + yield + i += 1 + branch_direction = yield dut.branch_direction_o # way branch went + (src1, src2, dest, op, (shadow_on, shadow_off)) = insts.pop(0) + if branch_direction == 1 and shadow_on: + print ("skip", i, src1, src2, dest, op, shadow_on, shadow_off) + continue # branch was "success" and this is a "failed"... skip + if branch_direction == 2 and shadow_off: + print ("skip", i, src1, src2, dest, op, shadow_on, shadow_off) + continue # branch was "fail" and this is a "success"... skip + if branch_direction != 0: + shadow_on = 0 + shadow_off = 0 + is_branch = op >= 4 + if is_branch: + branch_ok, branch_fail = dest + dest = src2 + # ok zip up the branch success / fail instructions and + # drop them into the queue, one marked "to have branch success" + # the other to be marked shadow branch "fail". + # one out of each of these will be cancelled + for ok, fl in zip(branch_ok, branch_fail): + if ok: + instrs.append((ok[0], ok[1], ok[2], ok[3], (1, 0))) + if fl: + instrs.append((fl[0], fl[1], fl[2], fl[3], (0, 1))) + print ("instr %d: (%d, %d, %d, %d, (%d, %d))" % \ + (i, src1, src2, dest, op, shadow_on, shadow_off)) + yield from int_instr(dut, op, src1, src2, dest, + shadow_on, shadow_off) + + # wait for all instructions to stop before checking + yield + yield from wait_for_busy_clear(dut) + + i = -1 + while siminsts: + instr = siminsts.pop(0) + if instr is None: + continue + (src1, src2, dest, op, (shadow_on, shadow_off)) = instr + i += 1 + is_branch = op >= 4 + if is_branch: + branch_ok, branch_fail = dest + dest = src2 + print ("sim %d: (%d, %d, %d, %d, (%d, %d))" % \ + (i, src1, src2, dest, op, shadow_on, shadow_off)) + branch_res = alusim.op(op, src1, src2, dest) + if is_branch: + if branch_res: + siminsts += branch_ok + else: + siminsts += branch_fail + + # check status + yield from alusim.check(dut) + yield from alusim.dump(dut) + + +def scoreboard_sim(dut, alusim): + + #seed(2) + + for i in range(1): + + # set random values in the registers + for i in range(1, dut.n_regs): + val = randint(0, (1<