X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fscore6600.py;h=2132a358bf6e23a1a42867e37de0b04c99f194de;hb=1bfd510f5fbd5abf2118ec0fe7516331523df732;hp=dd48f2d5bec4de653c3290002d869167c2645013;hpb=55f611806164b5b125ddcfa4732ec8c2d735e561;p=soc.git diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index dd48f2d5..2132a358 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -181,6 +181,7 @@ class CompUnitALUs(CompUnitsBase): # inputs self.oper_i = Signal(opwid, reset_less=True) + self.imm_i = Signal(rwid, reset_less=True) # Int ALUs add = ALU(rwid) @@ -190,7 +191,8 @@ class CompUnitALUs(CompUnitsBase): units = [] for alu in [add, sub, mul, shf]: - units.append(ComputationUnitNoDelay(rwid, 2, alu)) + aluopwid = 3 # extra bit for immediate mode + units.append(ComputationUnitNoDelay(rwid, aluopwid, alu)) CompUnitsBase.__init__(self, rwid, units) @@ -198,13 +200,10 @@ class CompUnitALUs(CompUnitsBase): m = CompUnitsBase.elaborate(self, platform) comb = m.d.comb - # hand the same operation to all units + # hand the same operation to all units, only lower 2 bits though for alu in self.units: - comb += alu.oper_i.eq(self.oper_i) - #comb += self.units[0].oper_i.eq(Const(0, 2)) # op=add - #comb += self.units[1].oper_i.eq(Const(1, 2)) # op=sub - #comb += self.units[2].oper_i.eq(Const(2, 2)) # op=mul - #comb += self.units[3].oper_i.eq(Const(3, 2)) # op=shf + comb += alu.oper_i[0:3].eq(self.oper_i) + comb += alu.imm_i.eq(self.imm_i) return m @@ -224,10 +223,12 @@ class CompUnitBR(CompUnitsBase): # inputs self.oper_i = Signal(opwid, reset_less=True) + self.imm_i = Signal(rwid, reset_less=True) # Branch ALU and CU self.bgt = BranchALU(rwid) - self.br1 = ComputationUnitNoDelay(rwid, 3, self.bgt) + aluopwid = 3 # extra bit for immediate mode + self.br1 = ComputationUnitNoDelay(rwid, aluopwid, self.bgt) CompUnitsBase.__init__(self, rwid, [self.br1]) def elaborate(self, platform): @@ -237,7 +238,7 @@ class CompUnitBR(CompUnitsBase): # hand the same operation to all units for alu in self.units: comb += alu.oper_i.eq(self.oper_i) - #comb += self.br1.oper_i.eq(Const(4, 3)) # op=bgt + comb += alu.imm_i.eq(self.imm_i) return m @@ -338,7 +339,9 @@ class Scoreboard(Elaboratable): self.brissue = IssueUnitGroup(1) # and these self.alu_oper_i = Signal(4, reset_less=True) + self.alu_imm_i = Signal(rwid, reset_less=True) self.br_oper_i = Signal(4, reset_less=True) + self.br_imm_i = Signal(rwid, reset_less=True) # inputs self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in @@ -377,8 +380,8 @@ class Scoreboard(Elaboratable): # Int ALUs and Comp Units n_int_alus = 5 - cua = CompUnitALUs(self.rwid, 2) - cub = CompUnitBR(self.rwid, 2) + cua = CompUnitALUs(self.rwid, 3) + cub = CompUnitBR(self.rwid, 3) m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub]) bgt = cub.bgt # get at the branch computation unit br1 = cub.br1 @@ -432,7 +435,9 @@ class Scoreboard(Elaboratable): # take these to outside (issue needs them) comb += cua.oper_i.eq(self.alu_oper_i) + comb += cua.imm_i.eq(self.alu_imm_i) comb += cub.oper_i.eq(self.br_oper_i) + comb += cub.imm_i.eq(self.br_imm_i) # TODO: issueunit.f (FP) @@ -589,6 +594,7 @@ class Scoreboard(Elaboratable): def ports(self): return list(self) + class IssueToScoreboard(Elaboratable): def __init__(self, qlen, n_in, n_out, rwid, opwid, n_regs): @@ -653,10 +659,12 @@ class IssueToScoreboard(Elaboratable): # "resetting" done above (insn_i=0) could be re-ASSERTed. with m.If(iq.qlen_o != 0): # get the operands and operation + imm = iq.data_o[0].imm_i dest = iq.data_o[0].dest_i src1 = iq.data_o[0].src1_i src2 = iq.data_o[0].src2_i op = iq.data_o[0].oper_i + opi = iq.data_o[0].opim_i # immediate set # set the src/dest regs comb += sc.int_dest_i.eq(dest) @@ -667,11 +675,13 @@ class IssueToScoreboard(Elaboratable): # choose a Function-Unit-Group with m.If((op & (0x3<<2)) != 0): # branch comb += sc.brissue.insn_i.eq(1) - comb += sc.br_oper_i.eq(op & 0x3) + comb += sc.br_oper_i.eq(Cat(op[0:2], opi)) + comb += sc.br_imm_i.eq(imm) comb += wait_issue_br.eq(1) with m.Else(): # alu comb += sc.aluissue.insn_i.eq(1) - comb += sc.alu_oper_i.eq(op & 0x3) + comb += sc.alu_oper_i.eq(Cat(op[0:2], opi)) + comb += sc.alu_imm_i.eq(imm) comb += wait_issue_alu.eq(1) # XXX TODO @@ -707,10 +717,13 @@ class RegSim: self.rwidth = rwidth self.regs = [0] * nregs - def op(self, op, src1, src2, dest): + def op(self, op, op_imm, imm, src1, src2, dest): maxbits = (1 << self.rwidth) - 1 src1 = self.regs[src1] & maxbits - src2 = self.regs[src2] & maxbits + if op_imm: + src2 = imm + else: + src2 = self.regs[src2] & maxbits if op == IADD: val = src1 + src2 elif op == ISUB: @@ -749,8 +762,10 @@ class RegSim: yield from self.dump(dut) assert False -def instr_q(dut, op, src1, src2, dest, branch_success, branch_fail): - instrs = [{'oper_i': op, 'dest_i': dest, 'src1_i': src1, 'src2_i': src2}] +def instr_q(dut, op, op_imm, imm, src1, src2, dest, + branch_success, branch_fail): + instrs = [{'oper_i': op, 'dest_i': dest, 'imm_i': imm, 'opim_i': op_imm, + 'src1_i': src1, 'src2_i': src2}] sendlen = 1 for idx in range(sendlen): @@ -767,7 +782,7 @@ def instr_q(dut, op, src1, src2, dest, branch_success, branch_fail): yield dut.p_add_i.eq(0) -def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail): +def int_instr(dut, op, imm, src1, src2, dest, branch_success, branch_fail): yield from disable_issue(dut) yield dut.int_dest_i.eq(dest) yield dut.int_src1_i.eq(src1) @@ -775,10 +790,12 @@ def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail): if (op & (0x3<<2)) != 0: # branch yield dut.brissue.insn_i.eq(1) yield dut.br_oper_i.eq(Const(op & 0x3, 2)) + yield dut.br_imm_i.eq(imm) dut_issue = dut.brissue else: yield dut.aluissue.insn_i.eq(1) yield dut.alu_oper_i.eq(Const(op & 0x3, 2)) + yield dut.alu_imm_i.eq(imm) dut_issue = dut.aluissue yield dut.reg_enable_i.eq(1) @@ -805,13 +822,15 @@ def create_random_ops(dut, n_ops, shadowing=False, max_opnums=3): for i in range(n_ops): src1 = randint(1, dut.n_regs-1) src2 = randint(1, dut.n_regs-1) + imm = randint(1, (1<