X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fscore6600.py;h=78ea09748ef66fca8a1c0d3d68b7fd7fb1c6ebc4;hb=c4a50df3d7f89890d9e6120de4448e4883efbc7b;hp=e3b4d5778486e252fb5a93d3c98d26c9e9884e5b;hpb=8feb26f6861f891021fdde1e03ecc4d8ee962a05;p=soc.git

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index e3b4d577..78ea0974 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -403,11 +403,14 @@ class Scoreboard(Elaboratable):
         # issue q needs to get at these
         self.aluissue = IssueUnitGroup(4)
         self.brissue = IssueUnitGroup(1)
+        self.lsissue = IssueUnitGroup(1)
         # and these
         self.alu_oper_i = Signal(4, reset_less=True)
         self.alu_imm_i = Signal(rwid, reset_less=True)
         self.br_oper_i = Signal(4, reset_less=True)
         self.br_imm_i = Signal(rwid, reset_less=True)
+        self.ls_oper_i = Signal(4, reset_less=True)
+        self.ls_imm_i = Signal(rwid, reset_less=True)
 
         # inputs
         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
@@ -446,12 +449,12 @@ class Scoreboard(Elaboratable):
 
         # Int ALUs and BR ALUs
         n_int_alus = 5
-        cua = CompUnitALUs(self.rwid, 3, n_alus=4)
+        cua = CompUnitALUs(self.rwid, 3, n_alus=2)
         cub = CompUnitBR(self.rwid, 3) # 1 BR ALUs
 
         # LDST Comp Units
         n_ldsts = 2
-        cul = CompUnitLDSTs(self.rwid, 3, None)
+        cul = CompUnitLDSTs(self.rwid, 4, None)
 
         # Comp Units
         m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub, cul])
@@ -475,7 +478,7 @@ class Scoreboard(Elaboratable):
         # INT/FP Issue Unit
         regdecode = RegDecode(self.n_regs)
         m.submodules.regdecode = regdecode
-        issueunit = IssueUnitArray([self.aluissue, self.brissue])
+        issueunit = IssueUnitArray([self.aluissue, self.brissue, self.lsissue])
         m.submodules.issueunit = issueunit
 
         # Shadow Matrix.  currently n_intfus shadows, to be used for
@@ -513,6 +516,8 @@ class Scoreboard(Elaboratable):
         comb += cua.imm_i.eq(self.alu_imm_i)
         comb += cub.oper_i.eq(self.br_oper_i)
         comb += cub.imm_i.eq(self.br_imm_i)
+        comb += cul.oper_i.eq(self.ls_oper_i)
+        comb += cul.imm_i.eq(self.ls_imm_i)
 
         # TODO: issueunit.f (FP)
 
@@ -618,9 +623,9 @@ class Scoreboard(Elaboratable):
         with m.If(br1.issue_i):
             sync += bspec.active_i.eq(1)
         with m.If(self.branch_succ_i):
-            comb += bspec.good_i.eq(fn_issue_o & 0x1f)
+            comb += bspec.good_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT
         with m.If(self.branch_fail_i):
-            comb += bspec.fail_i.eq(fn_issue_o & 0x1f)
+            comb += bspec.fail_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT
 
         # branch is active (TODO: a better signal: this is over-using the
         # go_write signal - actually the branch should not be "writing")
@@ -720,9 +725,13 @@ class IssueToScoreboard(Elaboratable):
         # in "waiting" state
         wait_issue_br = Signal()
         wait_issue_alu = Signal()
+        wait_issue_ls = Signal()
 
-        with m.If(wait_issue_br | wait_issue_alu):
+        with m.If(wait_issue_br | wait_issue_alu | wait_issue_ls):
             # set instruction pop length to 1 if the unit accepted
+            with m.If(wait_issue_ls & (sc.lsissue.fn_issue_o != 0)):
+                with m.If(iq.qlen_o != 0):
+                    comb += iq.n_sub_i.eq(1)
             with m.If(wait_issue_br & (sc.brissue.fn_issue_o != 0)):
                 with m.If(iq.qlen_o != 0):
                     comb += iq.n_sub_i.eq(1)
@@ -751,14 +760,24 @@ class IssueToScoreboard(Elaboratable):
 
             # choose a Function-Unit-Group
             with m.If((op & (0x3<<2)) != 0): # branch
-                comb += sc.brissue.insn_i.eq(1)
                 comb += sc.br_oper_i.eq(Cat(op[0:2], opi))
                 comb += sc.br_imm_i.eq(imm)
+                comb += sc.brissue.insn_i.eq(1)
                 comb += wait_issue_br.eq(1)
-            with m.Else():                   # alu
-                comb += sc.aluissue.insn_i.eq(1)
+            with m.Elif((op & (0x3<<4)) != 0): # ld/st
+                # see compldst.py
+                # bit 0: ADD/SUB
+                # bit 1: immed
+                # bit 4: LD
+                # bit 5: ST
+                comb += sc.ls_oper_i.eq(Cat(op[0], opi[0], op[4:6]))
+                comb += sc.ls_imm_i.eq(imm)
+                comb += sc.lsissue.insn_i.eq(1)
+                comb += wait_issue_ls.eq(1)
+            with m.Else(): # alu
                 comb += sc.alu_oper_i.eq(Cat(op[0:2], opi))
                 comb += sc.alu_imm_i.eq(imm)
+                comb += sc.aluissue.insn_i.eq(1)
                 comb += wait_issue_alu.eq(1)
 
             # XXX TODO
@@ -789,6 +808,7 @@ IBLT = 5
 IBEQ = 6
 IBNE = 7
 
+
 class RegSim:
     def __init__(self, rwidth, nregs):
         self.rwidth = rwidth
@@ -817,6 +837,8 @@ class RegSim:
             val = int(src1 == src2)
         elif op == IBNE:
             val = int(src1 != src2)
+        else:
+            return 0 # LD/ST TODO
         val &= maxbits
         self.setval(dest, val)
         return val
@@ -922,6 +944,7 @@ def wait_for_busy_clear(dut):
 def disable_issue(dut):
     yield dut.aluissue.insn_i.eq(0)
     yield dut.brissue.insn_i.eq(0)
+    yield dut.lsissue.insn_i.eq(0)
 
 
 def wait_for_issue(dut, dut_issue):
@@ -1066,9 +1089,12 @@ def scoreboard_sim(dut, alusim):
 
         # create some instructions (some random, some regression tests)
         instrs = []
-        if True:
+        if False:
             instrs = create_random_ops(dut, 15, True, 4)
 
+        if True: # LD test (with immediate)
+            instrs.append( (1, 2, 2, 0x10, 1, 20, (0, 0)) )
+
         if False:
             instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )