X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fscore6600.py;h=7c66f208c52d2f72828450564ef129e1ed299e95;hb=6018a7294c563e094e88583dc6d8558103d529e4;hp=9afdf0652bc351eaf2fd951a770d453f9f0ab0f0;hpb=5080334513c63819b3c8d522e2cd334ebc2d0307;p=soc.git diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 9afdf065..7c66f208 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -181,6 +181,7 @@ class CompUnitALUs(CompUnitsBase): # inputs self.oper_i = Signal(opwid, reset_less=True) + self.imm_i = Signal(rwid, reset_less=True) # Int ALUs add = ALU(rwid) @@ -201,7 +202,8 @@ class CompUnitALUs(CompUnitsBase): # hand the same operation to all units, only lower 2 bits though for alu in self.units: - comb += alu.oper_i[0:2].eq(self.oper_i) + comb += alu.oper_i[0:3].eq(self.oper_i) + comb += alu.imm_i.eq(self.imm_i) return m @@ -221,10 +223,12 @@ class CompUnitBR(CompUnitsBase): # inputs self.oper_i = Signal(opwid, reset_less=True) + self.imm_i = Signal(rwid, reset_less=True) # Branch ALU and CU self.bgt = BranchALU(rwid) - self.br1 = ComputationUnitNoDelay(rwid, 3, self.bgt) + aluopwid = 3 # extra bit for immediate mode + self.br1 = ComputationUnitNoDelay(rwid, aluopwid, self.bgt) CompUnitsBase.__init__(self, rwid, [self.br1]) def elaborate(self, platform): @@ -234,6 +238,7 @@ class CompUnitBR(CompUnitsBase): # hand the same operation to all units for alu in self.units: comb += alu.oper_i.eq(self.oper_i) + comb += alu.imm_i.eq(self.imm_i) return m @@ -255,14 +260,12 @@ class FunctionUnits(Elaboratable): self.src1_rsel_o = Signal(n_regs, reset_less=True) # src1 reg (bot) self.src2_rsel_o = Signal(n_regs, reset_less=True) # src2 reg (bot) - self.req_rel_i = Signal(n_int_alus, reset_less = True) self.readable_o = Signal(n_int_alus, reset_less=True) self.writable_o = Signal(n_int_alus, reset_less=True) self.go_rd_i = Signal(n_int_alus, reset_less=True) self.go_wr_i = Signal(n_int_alus, reset_less=True) self.go_die_i = Signal(n_int_alus, reset_less=True) - self.req_rel_o = Signal(n_int_alus, reset_less=True) self.fn_issue_i = Signal(n_int_alus, reset_less=True) # Note: FURegs wr_pend_o is also outputted from here, for use in WaWGrid @@ -278,14 +281,14 @@ class FunctionUnits(Elaboratable): intfudeps = FUFUDepMatrix(n_intfus, n_intfus) m.submodules.intfudeps = intfudeps # Integer FU-Reg Dep Matrix - intregdeps = FURegDepMatrix(n_intfus, self.n_regs) + intregdeps = FURegDepMatrix(n_intfus, self.n_regs, 2) m.submodules.intregdeps = intregdeps - comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o) - comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o) + comb += self.g_int_rd_pend_o.eq(intregdeps.v_rd_rsel_o) + comb += self.g_int_wr_pend_o.eq(intregdeps.v_wr_rsel_o) - comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o) - comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o) + comb += intregdeps.rd_pend_i.eq(intregdeps.v_rd_rsel_o) + comb += intregdeps.wr_pend_i.eq(intregdeps.v_wr_rsel_o) comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o) comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o) @@ -300,8 +303,8 @@ class FunctionUnits(Elaboratable): # Connect function issue / arrays, and dest/src1/src2 comb += intregdeps.dest_i.eq(self.dest_i) - comb += intregdeps.src1_i.eq(self.src1_i) - comb += intregdeps.src2_i.eq(self.src2_i) + comb += intregdeps.src_i[0].eq(self.src1_i) + comb += intregdeps.src_i[1].eq(self.src2_i) comb += intregdeps.go_rd_i.eq(self.go_rd_i) comb += intregdeps.go_wr_i.eq(self.go_wr_i) @@ -309,8 +312,8 @@ class FunctionUnits(Elaboratable): comb += intregdeps.issue_i.eq(self.fn_issue_i) comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o) - comb += self.src1_rsel_o.eq(intregdeps.src1_rsel_o) - comb += self.src2_rsel_o.eq(intregdeps.src2_rsel_o) + comb += self.src1_rsel_o.eq(intregdeps.src_rsel_o[0]) + comb += self.src2_rsel_o.eq(intregdeps.src_rsel_o[1]) return m @@ -334,7 +337,9 @@ class Scoreboard(Elaboratable): self.brissue = IssueUnitGroup(1) # and these self.alu_oper_i = Signal(4, reset_less=True) + self.alu_imm_i = Signal(rwid, reset_less=True) self.br_oper_i = Signal(4, reset_less=True) + self.br_imm_i = Signal(rwid, reset_less=True) # inputs self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in @@ -374,7 +379,7 @@ class Scoreboard(Elaboratable): # Int ALUs and Comp Units n_int_alus = 5 cua = CompUnitALUs(self.rwid, 3) - cub = CompUnitBR(self.rwid, 2) + cub = CompUnitBR(self.rwid, 3) m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub]) bgt = cub.bgt # get at the branch computation unit br1 = cub.br1 @@ -428,7 +433,9 @@ class Scoreboard(Elaboratable): # take these to outside (issue needs them) comb += cua.oper_i.eq(self.alu_oper_i) + comb += cua.imm_i.eq(self.alu_imm_i) comb += cub.oper_i.eq(self.br_oper_i) + comb += cub.imm_i.eq(self.br_imm_i) # TODO: issueunit.f (FP) @@ -650,6 +657,7 @@ class IssueToScoreboard(Elaboratable): # "resetting" done above (insn_i=0) could be re-ASSERTed. with m.If(iq.qlen_o != 0): # get the operands and operation + imm = iq.data_o[0].imm_i dest = iq.data_o[0].dest_i src1 = iq.data_o[0].src1_i src2 = iq.data_o[0].src2_i @@ -665,11 +673,13 @@ class IssueToScoreboard(Elaboratable): # choose a Function-Unit-Group with m.If((op & (0x3<<2)) != 0): # branch comb += sc.brissue.insn_i.eq(1) - comb += sc.br_oper_i.eq(op & 0x3) + comb += sc.br_oper_i.eq(Cat(op[0:2], opi)) + comb += sc.br_imm_i.eq(imm) comb += wait_issue_br.eq(1) with m.Else(): # alu comb += sc.aluissue.insn_i.eq(1) - comb += sc.alu_oper_i.eq(Cat(op & 0x3, opi)) + comb += sc.alu_oper_i.eq(Cat(op[0:2], opi)) + comb += sc.alu_imm_i.eq(imm) comb += wait_issue_alu.eq(1) # XXX TODO @@ -705,10 +715,12 @@ class RegSim: self.rwidth = rwidth self.regs = [0] * nregs - def op(self, op, op_imm, src1, src2, dest): + def op(self, op, op_imm, imm, src1, src2, dest): maxbits = (1 << self.rwidth) - 1 src1 = self.regs[src1] & maxbits - if not op_imm: # put op in src2 + if op_imm: + src2 = imm + else: src2 = self.regs[src2] & maxbits if op == IADD: val = src1 + src2 @@ -748,8 +760,9 @@ class RegSim: yield from self.dump(dut) assert False -def instr_q(dut, op, op_imm, src1, src2, dest, branch_success, branch_fail): - instrs = [{'oper_i': op, 'dest_i': dest, 'opim_i': op_imm, +def instr_q(dut, op, op_imm, imm, src1, src2, dest, + branch_success, branch_fail): + instrs = [{'oper_i': op, 'dest_i': dest, 'imm_i': imm, 'opim_i': op_imm, 'src1_i': src1, 'src2_i': src2}] sendlen = 1 @@ -767,7 +780,7 @@ def instr_q(dut, op, op_imm, src1, src2, dest, branch_success, branch_fail): yield dut.p_add_i.eq(0) -def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail): +def int_instr(dut, op, imm, src1, src2, dest, branch_success, branch_fail): yield from disable_issue(dut) yield dut.int_dest_i.eq(dest) yield dut.int_src1_i.eq(src1) @@ -775,10 +788,12 @@ def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail): if (op & (0x3<<2)) != 0: # branch yield dut.brissue.insn_i.eq(1) yield dut.br_oper_i.eq(Const(op & 0x3, 2)) + yield dut.br_imm_i.eq(imm) dut_issue = dut.brissue else: yield dut.aluissue.insn_i.eq(1) yield dut.alu_oper_i.eq(Const(op & 0x3, 2)) + yield dut.alu_imm_i.eq(imm) dut_issue = dut.aluissue yield dut.reg_enable_i.eq(1) @@ -805,14 +820,15 @@ def create_random_ops(dut, n_ops, shadowing=False, max_opnums=3): for i in range(n_ops): src1 = randint(1, dut.n_regs-1) src2 = randint(1, dut.n_regs-1) + imm = randint(1, (1<