X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fscore6600.py;h=e3b4d5778486e252fb5a93d3c98d26c9e9884e5b;hb=8feb26f6861f891021fdde1e03ecc4d8ee962a05;hp=ff2cf5d48921258d320951219366abdc2a80f3ba;hpb=1879f09123cf63bc170480d06d7373aaba10603c;p=soc.git

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index ff2cf5d4..e3b4d577 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
+from nmigen import Module, Const, Signal, Array, Cat, Elaboratable, Memory
 
 from regfile.regfile import RegFileArray, treereduce
 from scoreboard.fu_fu_matrix import FUFUDepMatrix
@@ -10,8 +10,10 @@ from scoreboard.group_picker import GroupPicker
 from scoreboard.issue_unit import IssueUnitGroup, IssueUnitArray, RegDecode
 from scoreboard.shadow import ShadowMatrix, BranchSpeculationRecord
 from scoreboard.instruction_q import Instruction, InstructionQ
+from scoreboard.memfu import MemFunctionUnits
 
 from compalu import ComputationUnitNoDelay
+from compldst import LDSTCompUnit
 
 from alu_hier import ALU, BranchALU
 from nmutil.latch import SRLatch
@@ -22,10 +24,10 @@ from copy import deepcopy
 from math import log
 
 
-class Memory(Elaboratable):
+class TestMemory(Elaboratable):
     def __init__(self, regwid, addrw):
-        self.ddepth = regwid/8
-        depth = (1<<addrw) / self.ddepth
+        self.ddepth = 1 # regwid //8
+        depth = (1<<addrw) // self.ddepth
         self.adr   = Signal(addrw)
         self.dat_r = Signal(regwid)
         self.dat_w = Signal(regwid)
@@ -49,7 +51,7 @@ class Memory(Elaboratable):
 class MemSim:
     def __init__(self, regwid, addrw):
         self.regwid = regwid
-        self.ddepth = regwid//8
+        self.ddepth = 1 # regwid//8
         depth = (1<<addrw) // self.ddepth
         self.mem = list(range(0, depth))
 
@@ -85,13 +87,14 @@ class CompUnitsBase(Elaboratable):
         Computation Unit" as defined by Mitch Alsup (see section
         11.4.9.3)
     """
-    def __init__(self, rwid, units):
+    def __init__(self, rwid, units, ldstmode=False):
         """ Inputs:
 
             * :rwid:   bit width of register file(s) - both FP and INT
             * :units: sequence of ALUs (or CompUnitsBase derivatives)
         """
         self.units = units
+        self.ldstmode = ldstmode
         self.rwid = rwid
         self.rwid = rwid
         if units and isinstance(units[0], CompUnitsBase):
@@ -109,11 +112,19 @@ class CompUnitsBase(Elaboratable):
         self.go_wr_i = Signal(n_units, reset_less=True)
         self.shadown_i = Signal(n_units, reset_less=True)
         self.go_die_i = Signal(n_units, reset_less=True)
+        if ldstmode:
+            self.go_ad_i = Signal(n_units, reset_less=True)
 
         # outputs
         self.busy_o = Signal(n_units, reset_less=True)
         self.rd_rel_o = Signal(n_units, reset_less=True)
         self.req_rel_o = Signal(n_units, reset_less=True)
+        if ldstmode:
+            self.adr_rel_o = Signal(n_units, reset_less=True)
+            self.sto_rel_o = Signal(n_units, reset_less=True)
+            self.req_rel_o = Signal(n_units, reset_less=True)
+            self.load_mem_o = Signal(n_units, reset_less=True)
+            self.stwd_mem_o = Signal(n_units, reset_less=True)
 
         # in/out register data (note: not register#, actual data)
         self.data_o = Signal(rwid, reset_less=True)
@@ -166,12 +177,70 @@ class CompUnitsBase(Elaboratable):
             comb += alu.src1_i.eq(self.src1_i)
             comb += alu.src2_i.eq(self.src2_i)
 
+        if not self.ldstmode:
+            return m
+
+        ldmem_l = []
+        stmem_l = []
+        go_ad_l = []
+        adr_rel_l = []
+        sto_rel_l = []
+        for alu in self.units:
+            adr_rel_l.append(alu.adr_rel_o)
+            sto_rel_l.append(alu.sto_rel_o)
+            ldmem_l.append(alu.load_mem_o)
+            stmem_l.append(alu.stwd_mem_o)
+            go_ad_l.append(alu.go_ad_i)
+        comb += self.adr_rel_o.eq(Cat(*adr_rel_l))
+        comb += self.sto_rel_o.eq(Cat(*sto_rel_l))
+        comb += self.load_mem_o.eq(Cat(*ldmem_l))
+        comb += self.stwd_mem_o.eq(Cat(*stmem_l))
+        comb += Cat(*go_ad_l).eq(self.go_ad_i)
+
+        return m
+
+
+class CompUnitLDSTs(CompUnitsBase):
+
+    def __init__(self, rwid, opwid, mem):
+        """ Inputs:
+
+            * :rwid:   bit width of register file(s) - both FP and INT
+            * :opwid:  operand bit width
+        """
+        self.opwid = opwid
+
+        # inputs
+        self.oper_i = Signal(opwid, reset_less=True)
+        self.imm_i = Signal(rwid, reset_less=True)
+
+        # Int ALUs
+        add1 = ALU(rwid)
+        add2 = ALU(rwid)
+
+        units = []
+        for alu in [add1, add2]:
+            aluopwid = 4 # see compldst.py for "internal" opcode
+            units.append(LDSTCompUnit(rwid, aluopwid, alu, mem))
+
+        CompUnitsBase.__init__(self, rwid, units, ldstmode=True)
+
+    def elaborate(self, platform):
+        m = CompUnitsBase.elaborate(self, platform)
+        comb = m.d.comb
+
+        # hand the same operation to all units, 4 lower bits though
+        for alu in self.units:
+            comb += alu.oper_i[0:4].eq(self.oper_i)
+            comb += alu.imm_i.eq(self.imm_i)
+            comb += alu.isalu_i.eq(0)
+
         return m
 
 
 class CompUnitALUs(CompUnitsBase):
 
-    def __init__(self, rwid, opwid):
+    def __init__(self, rwid, opwid, n_alus):
         """ Inputs:
 
             * :rwid:   bit width of register file(s) - both FP and INT
@@ -184,13 +253,12 @@ class CompUnitALUs(CompUnitsBase):
         self.imm_i = Signal(rwid, reset_less=True)
 
         # Int ALUs
-        add = ALU(rwid)
-        sub = ALU(rwid)
-        mul = ALU(rwid)
-        shf = ALU(rwid)
+        alus = []
+        for i in range(n_alus):
+            alus.append(ALU(rwid))
 
         units = []
-        for alu in [add, sub, mul, shf]:
+        for alu in alus:
             aluopwid = 3 # extra bit for immediate mode
             units.append(ComputationUnitNoDelay(rwid, aluopwid, alu))
 
@@ -200,7 +268,7 @@ class CompUnitALUs(CompUnitsBase):
         m = CompUnitsBase.elaborate(self, platform)
         comb = m.d.comb
 
-        # hand the same operation to all units, only lower 2 bits though
+        # hand the same operation to all units, only lower 3 bits though
         for alu in self.units:
             comb += alu.oper_i[0:3].eq(self.oper_i)
             comb += alu.imm_i.eq(self.imm_i)
@@ -223,10 +291,12 @@ class CompUnitBR(CompUnitsBase):
 
         # inputs
         self.oper_i = Signal(opwid, reset_less=True)
+        self.imm_i = Signal(rwid, reset_less=True)
 
         # Branch ALU and CU
         self.bgt = BranchALU(rwid)
-        self.br1 = ComputationUnitNoDelay(rwid, 3, self.bgt)
+        aluopwid = 3 # extra bit for immediate mode
+        self.br1 = ComputationUnitNoDelay(rwid, aluopwid, self.bgt)
         CompUnitsBase.__init__(self, rwid, [self.br1])
 
     def elaborate(self, platform):
@@ -236,6 +306,7 @@ class CompUnitBR(CompUnitsBase):
         # hand the same operation to all units
         for alu in self.units:
             comb += alu.oper_i.eq(self.oper_i)
+            comb += alu.imm_i.eq(self.imm_i)
 
         return m
 
@@ -257,14 +328,12 @@ class FunctionUnits(Elaboratable):
         self.src1_rsel_o = Signal(n_regs, reset_less=True) # src1 reg (bot)
         self.src2_rsel_o = Signal(n_regs, reset_less=True) # src2 reg (bot)
 
-        self.req_rel_i = Signal(n_int_alus, reset_less = True)
         self.readable_o = Signal(n_int_alus, reset_less=True)
         self.writable_o = Signal(n_int_alus, reset_less=True)
 
         self.go_rd_i = Signal(n_int_alus, reset_less=True)
         self.go_wr_i = Signal(n_int_alus, reset_less=True)
         self.go_die_i = Signal(n_int_alus, reset_less=True)
-        self.req_rel_o = Signal(n_int_alus, reset_less=True)
         self.fn_issue_i = Signal(n_int_alus, reset_less=True)
 
         # Note: FURegs wr_pend_o is also outputted from here, for use in WaWGrid
@@ -280,14 +349,14 @@ class FunctionUnits(Elaboratable):
         intfudeps = FUFUDepMatrix(n_intfus, n_intfus)
         m.submodules.intfudeps = intfudeps
         # Integer FU-Reg Dep Matrix
-        intregdeps = FURegDepMatrix(n_intfus, self.n_regs)
+        intregdeps = FURegDepMatrix(n_intfus, self.n_regs, 2)
         m.submodules.intregdeps = intregdeps
 
-        comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o)
-        comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o)
+        comb += self.g_int_rd_pend_o.eq(intregdeps.v_rd_rsel_o)
+        comb += self.g_int_wr_pend_o.eq(intregdeps.v_wr_rsel_o)
 
-        comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o)
-        comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o)
+        comb += intregdeps.rd_pend_i.eq(intregdeps.v_rd_rsel_o)
+        comb += intregdeps.wr_pend_i.eq(intregdeps.v_wr_rsel_o)
 
         comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
         comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
@@ -302,8 +371,8 @@ class FunctionUnits(Elaboratable):
 
         # Connect function issue / arrays, and dest/src1/src2
         comb += intregdeps.dest_i.eq(self.dest_i)
-        comb += intregdeps.src1_i.eq(self.src1_i)
-        comb += intregdeps.src2_i.eq(self.src2_i)
+        comb += intregdeps.src_i[0].eq(self.src1_i)
+        comb += intregdeps.src_i[1].eq(self.src2_i)
 
         comb += intregdeps.go_rd_i.eq(self.go_rd_i)
         comb += intregdeps.go_wr_i.eq(self.go_wr_i)
@@ -311,8 +380,8 @@ class FunctionUnits(Elaboratable):
         comb += intregdeps.issue_i.eq(self.fn_issue_i)
 
         comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o)
-        comb += self.src1_rsel_o.eq(intregdeps.src1_rsel_o)
-        comb += self.src2_rsel_o.eq(intregdeps.src2_rsel_o)
+        comb += self.src1_rsel_o.eq(intregdeps.src_rsel_o[0])
+        comb += self.src2_rsel_o.eq(intregdeps.src_rsel_o[1])
 
         return m
 
@@ -338,6 +407,7 @@ class Scoreboard(Elaboratable):
         self.alu_oper_i = Signal(4, reset_less=True)
         self.alu_imm_i = Signal(rwid, reset_less=True)
         self.br_oper_i = Signal(4, reset_less=True)
+        self.br_imm_i = Signal(rwid, reset_less=True)
 
         # inputs
         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
@@ -374,23 +444,32 @@ class Scoreboard(Elaboratable):
         fp_src1 = self.fpregs.read_port("src1")
         fp_src2 = self.fpregs.read_port("src2")
 
-        # Int ALUs and Comp Units
+        # Int ALUs and BR ALUs
         n_int_alus = 5
-        cua = CompUnitALUs(self.rwid, 3)
-        cub = CompUnitBR(self.rwid, 2)
-        m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub])
+        cua = CompUnitALUs(self.rwid, 3, n_alus=4)
+        cub = CompUnitBR(self.rwid, 3) # 1 BR ALUs
+
+        # LDST Comp Units
+        n_ldsts = 2
+        cul = CompUnitLDSTs(self.rwid, 3, None)
+
+        # Comp Units
+        m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub, cul])
         bgt = cub.bgt # get at the branch computation unit
         br1 = cub.br1
 
         # Int FUs
         m.submodules.intfus = intfus = FunctionUnits(self.n_regs, n_int_alus)
 
+        # Memory FUs
+        m.submodules.memfus = memfus = MemFunctionUnits(n_ldsts, 5)
+
         # Count of number of FUs
         n_intfus = n_int_alus
         n_fp_fus = 0 # for now
 
-        # Integer Priority Picker 1: Adder + Subtractor
-        intpick1 = GroupPicker(n_intfus) # picks between add, sub, mul and shf
+        # Integer Priority Picker 1: Adder + Subtractor (and LD/ST)
+        intpick1 = GroupPicker(n_intfus) # picks 1 reader and 1 writer to intreg
         m.submodules.intpick1 = intpick1
 
         # INT/FP Issue Unit
@@ -433,6 +512,7 @@ class Scoreboard(Elaboratable):
         comb += cua.oper_i.eq(self.alu_oper_i)
         comb += cua.imm_i.eq(self.alu_imm_i)
         comb += cub.oper_i.eq(self.br_oper_i)
+        comb += cub.imm_i.eq(self.br_imm_i)
 
         # TODO: issueunit.f (FP)
 
@@ -615,8 +695,10 @@ class IssueToScoreboard(Elaboratable):
 
         iq = InstructionQ(self.rwid, self.opw, self.qlen, self.n_in, self.n_out)
         sc = Scoreboard(self.rwid, self.n_regs)
+        mem = TestMemory(self.rwid, 8) # not too big, takes too long
         m.submodules.iq = iq
         m.submodules.sc = sc
+        m.submodules.mem = mem
 
         # get at the regfile for testing
         self.intregs = sc.intregs
@@ -670,7 +752,8 @@ class IssueToScoreboard(Elaboratable):
             # choose a Function-Unit-Group
             with m.If((op & (0x3<<2)) != 0): # branch
                 comb += sc.brissue.insn_i.eq(1)
-                comb += sc.br_oper_i.eq(op & 0x3)
+                comb += sc.br_oper_i.eq(Cat(op[0:2], opi))
+                comb += sc.br_imm_i.eq(imm)
                 comb += wait_issue_br.eq(1)
             with m.Else():                   # alu
                 comb += sc.aluissue.insn_i.eq(1)
@@ -784,6 +867,7 @@ def int_instr(dut, op, imm, src1, src2, dest, branch_success, branch_fail):
     if (op & (0x3<<2)) != 0: # branch
         yield dut.brissue.insn_i.eq(1)
         yield dut.br_oper_i.eq(Const(op & 0x3, 2))
+        yield dut.br_imm_i.eq(imm)
         dut_issue = dut.brissue
     else:
         yield dut.aluissue.insn_i.eq(1)
@@ -968,7 +1052,7 @@ def scoreboard_branch_sim(dut, alusim):
 
 def scoreboard_sim(dut, alusim):
 
-    #seed(2)
+    seed(0)
 
     for i in range(1):
 
@@ -983,7 +1067,7 @@ def scoreboard_sim(dut, alusim):
         # create some instructions (some random, some regression tests)
         instrs = []
         if True:
-            instrs = create_random_ops(dut, 15, True, 3)
+            instrs = create_random_ops(dut, 15, True, 4)
 
         if False:
             instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )
@@ -993,13 +1077,17 @@ def scoreboard_sim(dut, alusim):
             instrs.append( (7, 6, 6, 2, (0, 0)) )
             instrs.append( (1, 7, 2, 2, (0, 0)) )
 
+        if False:
+            instrs.append((2, 3, 3, 0, 0, 0, (0, 0)))
+            instrs.append((5, 3, 3, 1, 0, 0, (0, 0)))
+            instrs.append((3, 5, 5, 2, 0, 0, (0, 0)))
+            instrs.append((5, 3, 3, 3, 0, 0, (0, 0)))
+            instrs.append((3, 5, 5, 0, 0, 0, (0, 0)))
 
         if False:
-            instrs.append((2, 3, 3, 0, (0, 0)))
-            instrs.append((5, 3, 3, 1, (0, 0)))
-            instrs.append((3, 5, 5, 2, (0, 0)))
-            instrs.append((5, 3, 3, 3, (0, 0)))
-            instrs.append((3, 5, 5, 0, (0, 0)))
+            instrs.append( (3, 3, 4, 0, 0, 13979, (0, 0)))
+            instrs.append( (6, 4, 1, 2, 0, 40976, (0, 0)))
+            instrs.append( (1, 4, 7, 4, 1, 23652, (0, 0)))
 
         if False:
             instrs.append((5, 6, 2, 1))