X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fscore6600.py;h=ed953e8b71a3b80ff82fde4c93a115d8fcd39303;hb=9160489ce48a008af3e07fdc81d458a0b366f997;hp=4ed9acbd1aa215b05a61046979426ad7bd32bdb8;hpb=cf8a2129f2622c99e28703a9049e697ec83b67f2;p=soc.git

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 4ed9acbd..ed953e8b 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
+from nmigen import Module, Const, Signal, Array, Cat, Elaboratable, Memory
 
 from regfile.regfile import RegFileArray, treereduce
 from scoreboard.fu_fu_matrix import FUFUDepMatrix
@@ -10,8 +10,10 @@ from scoreboard.group_picker import GroupPicker
 from scoreboard.issue_unit import IssueUnitGroup, IssueUnitArray, RegDecode
 from scoreboard.shadow import ShadowMatrix, BranchSpeculationRecord
 from scoreboard.instruction_q import Instruction, InstructionQ
+from scoreboard.memfu import MemFunctionUnits
 
 from compalu import ComputationUnitNoDelay
+from compldst import LDSTCompUnit
 
 from alu_hier import ALU, BranchALU
 from nmutil.latch import SRLatch
@@ -22,6 +24,44 @@ from copy import deepcopy
 from math import log
 
 
+class TestMemory(Elaboratable):
+    def __init__(self, regwid, addrw):
+        self.ddepth = 1 # regwid //8
+        depth = (1<<addrw) // self.ddepth
+        self.adr   = Signal(addrw)
+        self.dat_r = Signal(regwid)
+        self.dat_w = Signal(regwid)
+        self.we    = Signal()
+        self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.rdport = rdport = self.mem.read_port()
+        m.submodules.wrport = wrport = self.mem.write_port()
+        m.d.comb += [
+            rdport.addr.eq(self.adr[self.ddepth:]), # ignore low bits
+            self.dat_r.eq(rdport.data),
+            wrport.addr.eq(self.adr),
+            wrport.data.eq(self.dat_w),
+            wrport.en.eq(self.we),
+        ]
+        return m
+
+
+class MemSim:
+    def __init__(self, regwid, addrw):
+        self.regwid = regwid
+        self.ddepth = 1 # regwid//8
+        depth = (1<<addrw) // self.ddepth
+        self.mem = list(range(0, depth))
+
+    def ld(self, addr):
+        return self.mem[addr>>self.ddepth]
+
+    def st(self, addr, data):
+        self.mem[addr>>self.ddepth] = data & ((1<<self.regwid)-1)
+
+
 class CompUnitsBase(Elaboratable):
     """ Computation Unit Base class.
 
@@ -47,13 +87,14 @@ class CompUnitsBase(Elaboratable):
         Computation Unit" as defined by Mitch Alsup (see section
         11.4.9.3)
     """
-    def __init__(self, rwid, units):
+    def __init__(self, rwid, units, ldstmode=False):
         """ Inputs:
 
             * :rwid:   bit width of register file(s) - both FP and INT
             * :units: sequence of ALUs (or CompUnitsBase derivatives)
         """
         self.units = units
+        self.ldstmode = ldstmode
         self.rwid = rwid
         self.rwid = rwid
         if units and isinstance(units[0], CompUnitsBase):
@@ -71,11 +112,19 @@ class CompUnitsBase(Elaboratable):
         self.go_wr_i = Signal(n_units, reset_less=True)
         self.shadown_i = Signal(n_units, reset_less=True)
         self.go_die_i = Signal(n_units, reset_less=True)
+        if ldstmode:
+            self.go_ad_i = Signal(n_units, reset_less=True)
 
         # outputs
         self.busy_o = Signal(n_units, reset_less=True)
         self.rd_rel_o = Signal(n_units, reset_less=True)
         self.req_rel_o = Signal(n_units, reset_less=True)
+        if ldstmode:
+            self.adr_rel_o = Signal(n_units, reset_less=True)
+            self.sto_rel_o = Signal(n_units, reset_less=True)
+            self.req_rel_o = Signal(n_units, reset_less=True)
+            self.load_mem_o = Signal(n_units, reset_less=True)
+            self.stwd_mem_o = Signal(n_units, reset_less=True)
 
         # in/out register data (note: not register#, actual data)
         self.data_o = Signal(rwid, reset_less=True)
@@ -128,12 +177,71 @@ class CompUnitsBase(Elaboratable):
             comb += alu.src1_i.eq(self.src1_i)
             comb += alu.src2_i.eq(self.src2_i)
 
+        if not self.ldstmode:
+            return m
+
+        ldmem_l = []
+        stmem_l = []
+        go_ad_l = []
+        adr_rel_l = []
+        sto_rel_l = []
+        for alu in self.units:
+            adr_rel_l.append(alu.adr_rel_o)
+            sto_rel_l.append(alu.sto_rel_o)
+            ldmem_l.append(alu.load_mem_o)
+            stmem_l.append(alu.stwd_mem_o)
+            go_ad_l.append(alu.go_ad_i)
+        comb += self.adr_rel_o.eq(Cat(*adr_rel_l))
+        comb += self.sto_rel_o.eq(Cat(*sto_rel_l))
+        comb += self.load_mem_o.eq(Cat(*ldmem_l))
+        comb += self.stwd_mem_o.eq(Cat(*stmem_l))
+        comb += Cat(*go_ad_l).eq(self.go_ad_i)
+
+        return m
+
+
+class CompUnitLDSTs(CompUnitsBase):
+
+    def __init__(self, rwid, opwid, n_ldsts, mem):
+        """ Inputs:
+
+            * :rwid:   bit width of register file(s) - both FP and INT
+            * :opwid:  operand bit width
+        """
+        self.opwid = opwid
+
+        # inputs
+        self.oper_i = Signal(opwid, reset_less=True)
+        self.imm_i = Signal(rwid, reset_less=True)
+
+        # Int ALUs
+        self.alus = []
+        for i in range(n_ldsts):
+            self.alus.append(ALU(rwid))
+
+        units = []
+        for alu in self.alus:
+            aluopwid = 4 # see compldst.py for "internal" opcode
+            units.append(LDSTCompUnit(rwid, aluopwid, alu, mem))
+
+        CompUnitsBase.__init__(self, rwid, units, ldstmode=True)
+
+    def elaborate(self, platform):
+        m = CompUnitsBase.elaborate(self, platform)
+        comb = m.d.comb
+
+        # hand the same operation to all units, 4 lower bits though
+        for alu in self.units:
+            comb += alu.oper_i[0:4].eq(self.oper_i)
+            comb += alu.imm_i.eq(self.imm_i)
+            comb += alu.isalu_i.eq(0)
+
         return m
 
 
 class CompUnitALUs(CompUnitsBase):
 
-    def __init__(self, rwid, opwid):
+    def __init__(self, rwid, opwid, n_alus):
         """ Inputs:
 
             * :rwid:   bit width of register file(s) - both FP and INT
@@ -143,16 +251,17 @@ class CompUnitALUs(CompUnitsBase):
 
         # inputs
         self.oper_i = Signal(opwid, reset_less=True)
+        self.imm_i = Signal(rwid, reset_less=True)
 
         # Int ALUs
-        add = ALU(rwid)
-        sub = ALU(rwid)
-        mul = ALU(rwid)
-        shf = ALU(rwid)
+        alus = []
+        for i in range(n_alus):
+            alus.append(ALU(rwid))
 
         units = []
-        for alu in [add, sub, mul, shf]:
-            units.append(ComputationUnitNoDelay(rwid, 2, alu))
+        for alu in alus:
+            aluopwid = 3 # extra bit for immediate mode
+            units.append(ComputationUnitNoDelay(rwid, aluopwid, alu))
 
         CompUnitsBase.__init__(self, rwid, units)
 
@@ -160,13 +269,10 @@ class CompUnitALUs(CompUnitsBase):
         m = CompUnitsBase.elaborate(self, platform)
         comb = m.d.comb
 
-        # hand the same operation to all units
+        # hand the same operation to all units, only lower 3 bits though
         for alu in self.units:
-            comb += alu.oper_i.eq(self.oper_i)
-        #comb += self.units[0].oper_i.eq(Const(0, 2)) # op=add
-        #comb += self.units[1].oper_i.eq(Const(1, 2)) # op=sub
-        #comb += self.units[2].oper_i.eq(Const(2, 2)) # op=mul
-        #comb += self.units[3].oper_i.eq(Const(3, 2)) # op=shf
+            comb += alu.oper_i[0:3].eq(self.oper_i)
+            comb += alu.imm_i.eq(self.imm_i)
 
         return m
 
@@ -186,10 +292,12 @@ class CompUnitBR(CompUnitsBase):
 
         # inputs
         self.oper_i = Signal(opwid, reset_less=True)
+        self.imm_i = Signal(rwid, reset_less=True)
 
         # Branch ALU and CU
         self.bgt = BranchALU(rwid)
-        self.br1 = ComputationUnitNoDelay(rwid, 3, self.bgt)
+        aluopwid = 3 # extra bit for immediate mode
+        self.br1 = ComputationUnitNoDelay(rwid, aluopwid, self.bgt)
         CompUnitsBase.__init__(self, rwid, [self.br1])
 
     def elaborate(self, platform):
@@ -199,7 +307,7 @@ class CompUnitBR(CompUnitsBase):
         # hand the same operation to all units
         for alu in self.units:
             comb += alu.oper_i.eq(self.oper_i)
-        #comb += self.br1.oper_i.eq(Const(4, 3)) # op=bgt
+            comb += alu.imm_i.eq(self.imm_i)
 
         return m
 
@@ -221,14 +329,12 @@ class FunctionUnits(Elaboratable):
         self.src1_rsel_o = Signal(n_regs, reset_less=True) # src1 reg (bot)
         self.src2_rsel_o = Signal(n_regs, reset_less=True) # src2 reg (bot)
 
-        self.req_rel_i = Signal(n_int_alus, reset_less = True)
         self.readable_o = Signal(n_int_alus, reset_less=True)
         self.writable_o = Signal(n_int_alus, reset_less=True)
 
         self.go_rd_i = Signal(n_int_alus, reset_less=True)
         self.go_wr_i = Signal(n_int_alus, reset_less=True)
         self.go_die_i = Signal(n_int_alus, reset_less=True)
-        self.req_rel_o = Signal(n_int_alus, reset_less=True)
         self.fn_issue_i = Signal(n_int_alus, reset_less=True)
 
         # Note: FURegs wr_pend_o is also outputted from here, for use in WaWGrid
@@ -244,14 +350,14 @@ class FunctionUnits(Elaboratable):
         intfudeps = FUFUDepMatrix(n_intfus, n_intfus)
         m.submodules.intfudeps = intfudeps
         # Integer FU-Reg Dep Matrix
-        intregdeps = FURegDepMatrix(n_intfus, self.n_regs)
+        intregdeps = FURegDepMatrix(n_intfus, self.n_regs, 2)
         m.submodules.intregdeps = intregdeps
 
-        comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o)
-        comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o)
+        comb += self.g_int_rd_pend_o.eq(intregdeps.v_rd_rsel_o)
+        comb += self.g_int_wr_pend_o.eq(intregdeps.v_wr_rsel_o)
 
-        comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o)
-        comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o)
+        comb += intregdeps.rd_pend_i.eq(intregdeps.v_rd_rsel_o)
+        comb += intregdeps.wr_pend_i.eq(intregdeps.v_wr_rsel_o)
 
         comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
         comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
@@ -266,8 +372,8 @@ class FunctionUnits(Elaboratable):
 
         # Connect function issue / arrays, and dest/src1/src2
         comb += intregdeps.dest_i.eq(self.dest_i)
-        comb += intregdeps.src1_i.eq(self.src1_i)
-        comb += intregdeps.src2_i.eq(self.src2_i)
+        comb += intregdeps.src_i[0].eq(self.src1_i)
+        comb += intregdeps.src_i[1].eq(self.src2_i)
 
         comb += intregdeps.go_rd_i.eq(self.go_rd_i)
         comb += intregdeps.go_wr_i.eq(self.go_wr_i)
@@ -275,8 +381,8 @@ class FunctionUnits(Elaboratable):
         comb += intregdeps.issue_i.eq(self.fn_issue_i)
 
         comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o)
-        comb += self.src1_rsel_o.eq(intregdeps.src1_rsel_o)
-        comb += self.src2_rsel_o.eq(intregdeps.src2_rsel_o)
+        comb += self.src1_rsel_o.eq(intregdeps.src_rsel_o[0])
+        comb += self.src2_rsel_o.eq(intregdeps.src_rsel_o[1])
 
         return m
 
@@ -296,11 +402,16 @@ class Scoreboard(Elaboratable):
         self.fpregs = RegFileArray(rwid, n_regs)
 
         # issue q needs to get at these
-        self.aluissue = IssueUnitGroup(4)
+        self.aluissue = IssueUnitGroup(2)
+        self.lsissue = IssueUnitGroup(2)
         self.brissue = IssueUnitGroup(1)
         # and these
         self.alu_oper_i = Signal(4, reset_less=True)
+        self.alu_imm_i = Signal(rwid, reset_less=True)
         self.br_oper_i = Signal(4, reset_less=True)
+        self.br_imm_i = Signal(rwid, reset_less=True)
+        self.ls_oper_i = Signal(4, reset_less=True)
+        self.ls_imm_i = Signal(rwid, reset_less=True)
 
         # inputs
         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
@@ -337,29 +448,38 @@ class Scoreboard(Elaboratable):
         fp_src1 = self.fpregs.read_port("src1")
         fp_src2 = self.fpregs.read_port("src2")
 
-        # Int ALUs and Comp Units
+        # Int ALUs and BR ALUs
         n_int_alus = 5
-        cua = CompUnitALUs(self.rwid, 2)
-        cub = CompUnitBR(self.rwid, 2)
-        m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub])
+        cua = CompUnitALUs(self.rwid, 3, n_alus=self.aluissue.n_insns)
+        cub = CompUnitBR(self.rwid, 3) # 1 BR ALUs
+
+        # LDST Comp Units
+        n_ldsts = 2
+        cul = CompUnitLDSTs(self.rwid, 4, self.lsissue.n_insns, None)
+
+        # Comp Units
+        m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cul, cub])
         bgt = cub.bgt # get at the branch computation unit
         br1 = cub.br1
 
         # Int FUs
         m.submodules.intfus = intfus = FunctionUnits(self.n_regs, n_int_alus)
 
+        # Memory FUs
+        m.submodules.memfus = memfus = MemFunctionUnits(n_ldsts, 5)
+
         # Count of number of FUs
         n_intfus = n_int_alus
         n_fp_fus = 0 # for now
 
-        # Integer Priority Picker 1: Adder + Subtractor
-        intpick1 = GroupPicker(n_intfus) # picks between add, sub, mul and shf
+        # Integer Priority Picker 1: Adder + Subtractor (and LD/ST)
+        intpick1 = GroupPicker(n_intfus) # picks 1 reader and 1 writer to intreg
         m.submodules.intpick1 = intpick1
 
         # INT/FP Issue Unit
         regdecode = RegDecode(self.n_regs)
         m.submodules.regdecode = regdecode
-        issueunit = IssueUnitArray([self.aluissue, self.brissue])
+        issueunit = IssueUnitArray([self.aluissue, self.lsissue, self.brissue])
         m.submodules.issueunit = issueunit
 
         # Shadow Matrix.  currently n_intfus shadows, to be used for
@@ -369,7 +489,6 @@ class Scoreboard(Elaboratable):
         m.submodules.bshadow = bshadow = ShadowMatrix(n_intfus, 1, False)
 
         # record previous instruction to cast shadow on current instruction
-        fn_issue_prev = Signal(n_intfus)
         prev_shadow = Signal(n_intfus)
 
         # Branch Speculation recorder.  tracks the success/fail state as
@@ -395,7 +514,11 @@ class Scoreboard(Elaboratable):
 
         # take these to outside (issue needs them)
         comb += cua.oper_i.eq(self.alu_oper_i)
+        comb += cua.imm_i.eq(self.alu_imm_i)
         comb += cub.oper_i.eq(self.br_oper_i)
+        comb += cub.imm_i.eq(self.br_imm_i)
+        comb += cul.oper_i.eq(self.ls_oper_i)
+        comb += cul.imm_i.eq(self.ls_imm_i)
 
         # TODO: issueunit.f (FP)
 
@@ -410,6 +533,19 @@ class Scoreboard(Elaboratable):
         comb += issueunit.busy_i.eq(cu.busy_o)
         comb += self.busy_o.eq(cu.busy_o.bool())
 
+        #---------
+        # Memory Function Unit
+        #---------
+        comb += memfus.fn_issue_i.eq(cul.issue_i) # Comp Unit Issue -> Mem FUs
+        comb += memfus.addr_we_i.eq(cul.adr_rel_o) # Match enable on adr rel
+
+        comb += memfus.addrs_i[0].eq(cul.units[0].data_o)
+        comb += memfus.addrs_i[1].eq(cul.units[1].data_o)
+
+        #comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus])
+        #comb += cu.go_wr_i[0:n_intfus].eq(go_wr_o[0:n_intfus])
+        #comb += cu.issue_i[0:n_intfus].eq(fn_issue_o[0:n_intfus])
+
         #---------
         # merge shadow matrices outputs
         #---------
@@ -470,10 +606,6 @@ class Scoreboard(Elaboratable):
         for i in range(n_intfus):
             comb += shadows.s_good_i[i][0:n_intfus].eq(go_wr_o[0:n_intfus])
 
-        # work out the current-activated busy unit (by recording the old one)
-        with m.If(fn_issue_o): # only update prev bit if instruction issued
-            sync += fn_issue_prev.eq(fn_issue_o)
-
         # *previous* instruction shadows *current* instruction, and, obviously,
         # if the previous is completed (!busy) don't cast the shadow!
         comb += prev_shadow.eq(~fn_issue_o & cu.busy_o)
@@ -505,9 +637,9 @@ class Scoreboard(Elaboratable):
         with m.If(br1.issue_i):
             sync += bspec.active_i.eq(1)
         with m.If(self.branch_succ_i):
-            comb += bspec.good_i.eq(fn_issue_o & 0x1f)
+            comb += bspec.good_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT
         with m.If(self.branch_fail_i):
-            comb += bspec.fail_i.eq(fn_issue_o & 0x1f)
+            comb += bspec.fail_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT
 
         # branch is active (TODO: a better signal: this is over-using the
         # go_write signal - actually the branch should not be "writing")
@@ -556,6 +688,7 @@ class Scoreboard(Elaboratable):
     def ports(self):
         return list(self)
 
+
 class IssueToScoreboard(Elaboratable):
 
     def __init__(self, qlen, n_in, n_out, rwid, opwid, n_regs):
@@ -581,8 +714,10 @@ class IssueToScoreboard(Elaboratable):
 
         iq = InstructionQ(self.rwid, self.opw, self.qlen, self.n_in, self.n_out)
         sc = Scoreboard(self.rwid, self.n_regs)
+        mem = TestMemory(self.rwid, 8) # not too big, takes too long
         m.submodules.iq = iq
         m.submodules.sc = sc
+        m.submodules.mem = mem
 
         # get at the regfile for testing
         self.intregs = sc.intregs
@@ -604,29 +739,19 @@ class IssueToScoreboard(Elaboratable):
         # in "waiting" state
         wait_issue_br = Signal()
         wait_issue_alu = Signal()
+        wait_issue_ls = Signal()
 
-        with m.If(wait_issue_br | wait_issue_alu):
+        with m.If(wait_issue_br | wait_issue_alu | wait_issue_ls):
             # set instruction pop length to 1 if the unit accepted
-            # also tell the unit-group to stop accepting the instruction
-            # and disable the regfile
+            with m.If(wait_issue_ls & (sc.lsissue.fn_issue_o != 0)):
+                with m.If(iq.qlen_o != 0):
+                    comb += iq.n_sub_i.eq(1)
             with m.If(wait_issue_br & (sc.brissue.fn_issue_o != 0)):
                 with m.If(iq.qlen_o != 0):
                     comb += iq.n_sub_i.eq(1)
-                comb += wait_issue_br.eq(0)
-                comb += sc.brissue.insn_i.eq(0)
-                comb += sc.int_dest_i.eq(0)
-                comb += sc.int_src1_i.eq(0)
-                comb += sc.int_src2_i.eq(0)
-                comb += sc.reg_enable_i.eq(0)
             with m.If(wait_issue_alu & (sc.aluissue.fn_issue_o != 0)):
                 with m.If(iq.qlen_o != 0):
                     comb += iq.n_sub_i.eq(1)
-                comb += wait_issue_alu.eq(0)
-                comb += sc.aluissue.insn_i.eq(0)
-                comb += sc.int_dest_i.eq(0)
-                comb += sc.int_src1_i.eq(0)
-                comb += sc.int_src2_i.eq(0)
-                comb += sc.reg_enable_i.eq(0)
 
         # see if some instruction(s) are here.  note that this is
         # "inspecting" the in-place queue.  note also that on the
@@ -634,10 +759,12 @@ class IssueToScoreboard(Elaboratable):
         # "resetting" done above (insn_i=0) could be re-ASSERTed.
         with m.If(iq.qlen_o != 0):
             # get the operands and operation
+            imm = iq.data_o[0].imm_i
             dest = iq.data_o[0].dest_i
             src1 = iq.data_o[0].src1_i
             src2 = iq.data_o[0].src2_i
             op = iq.data_o[0].oper_i
+            opi = iq.data_o[0].opim_i # immediate set
 
             # set the src/dest regs
             comb += sc.int_dest_i.eq(dest)
@@ -647,12 +774,24 @@ class IssueToScoreboard(Elaboratable):
 
             # choose a Function-Unit-Group
             with m.If((op & (0x3<<2)) != 0): # branch
+                comb += sc.br_oper_i.eq(Cat(op[0:2], opi))
+                comb += sc.br_imm_i.eq(imm)
                 comb += sc.brissue.insn_i.eq(1)
-                comb += sc.br_oper_i.eq(op & 0x3)
                 comb += wait_issue_br.eq(1)
-            with m.Else():                   # alu
+            with m.Elif((op & (0x3<<4)) != 0): # ld/st
+                # see compldst.py
+                # bit 0: ADD/SUB
+                # bit 1: immed
+                # bit 4: LD
+                # bit 5: ST
+                comb += sc.ls_oper_i.eq(Cat(op[0], opi[0], op[4:6]))
+                comb += sc.ls_imm_i.eq(imm)
+                comb += sc.lsissue.insn_i.eq(1)
+                comb += wait_issue_ls.eq(1)
+            with m.Else(): # alu
+                comb += sc.alu_oper_i.eq(Cat(op[0:2], opi))
+                comb += sc.alu_imm_i.eq(imm)
                 comb += sc.aluissue.insn_i.eq(1)
-                comb += sc.alu_oper_i.eq(op & 0x3)
                 comb += wait_issue_alu.eq(1)
 
             # XXX TODO
@@ -673,6 +812,7 @@ class IssueToScoreboard(Elaboratable):
     def ports(self):
         return list(self)
 
+
 IADD = 0
 ISUB = 1
 IMUL = 2
@@ -682,15 +822,19 @@ IBLT = 5
 IBEQ = 6
 IBNE = 7
 
+
 class RegSim:
     def __init__(self, rwidth, nregs):
         self.rwidth = rwidth
         self.regs = [0] * nregs
 
-    def op(self, op, src1, src2, dest):
+    def op(self, op, op_imm, imm, src1, src2, dest):
         maxbits = (1 << self.rwidth) - 1
         src1 = self.regs[src1] & maxbits
-        src2 = self.regs[src2] & maxbits
+        if op_imm:
+            src2 = imm
+        else:
+            src2 = self.regs[src2] & maxbits
         if op == IADD:
             val = src1 + src2
         elif op == ISUB:
@@ -707,6 +851,8 @@ class RegSim:
             val = int(src1 == src2)
         elif op == IBNE:
             val = int(src1 != src2)
+        else:
+            return 0 # LD/ST TODO
         val &= maxbits
         self.setval(dest, val)
         return val
@@ -729,8 +875,10 @@ class RegSim:
                 yield from self.dump(dut)
                 assert False
 
-def instr_q(dut, op, src1, src2, dest, branch_success, branch_fail):
-    instrs = [{'oper_i': op, 'dest_i': dest, 'src1_i': src1, 'src2_i': src2}]
+def instr_q(dut, op, op_imm, imm, src1, src2, dest,
+            branch_success, branch_fail):
+    instrs = [{'oper_i': op, 'dest_i': dest, 'imm_i': imm, 'opim_i': op_imm,
+               'src1_i': src1, 'src2_i': src2}]
 
     sendlen = 1
     for idx in range(sendlen):
@@ -747,7 +895,7 @@ def instr_q(dut, op, src1, src2, dest, branch_success, branch_fail):
     yield dut.p_add_i.eq(0)
 
 
-def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail):
+def int_instr(dut, op, imm, src1, src2, dest, branch_success, branch_fail):
     yield from disable_issue(dut)
     yield dut.int_dest_i.eq(dest)
     yield dut.int_src1_i.eq(src1)
@@ -755,10 +903,12 @@ def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail):
     if (op & (0x3<<2)) != 0: # branch
         yield dut.brissue.insn_i.eq(1)
         yield dut.br_oper_i.eq(Const(op & 0x3, 2))
+        yield dut.br_imm_i.eq(imm)
         dut_issue = dut.brissue
     else:
         yield dut.aluissue.insn_i.eq(1)
         yield dut.alu_oper_i.eq(Const(op & 0x3, 2))
+        yield dut.alu_imm_i.eq(imm)
         dut_issue = dut.aluissue
     yield dut.reg_enable_i.eq(1)
 
@@ -785,13 +935,15 @@ def create_random_ops(dut, n_ops, shadowing=False, max_opnums=3):
     for i in range(n_ops):
         src1 = randint(1, dut.n_regs-1)
         src2 = randint(1, dut.n_regs-1)
+        imm = randint(1, (1<<dut.rwid)-1)
         dest = randint(1, dut.n_regs-1)
         op = randint(0, max_opnums)
+        opi = 0 if randint(0, 2) else 1 # set true if random is nonzero
 
         if shadowing:
-            insts.append((src1, src2, dest, op, (0, 0)))
+            insts.append((src1, src2, dest, op, opi, imm, (0, 0)))
         else:
-            insts.append((src1, src2, dest, op))
+            insts.append((src1, src2, dest, op, opi, imm))
     return insts
 
 
@@ -806,6 +958,7 @@ def wait_for_busy_clear(dut):
 def disable_issue(dut):
     yield dut.aluissue.insn_i.eq(0)
     yield dut.brissue.insn_i.eq(0)
+    yield dut.lsissue.insn_i.eq(0)
 
 
 def wait_for_issue(dut, dut_issue):
@@ -936,7 +1089,7 @@ def scoreboard_branch_sim(dut, alusim):
 
 def scoreboard_sim(dut, alusim):
 
-    #seed(2)
+    seed(0)
 
     for i in range(1):
 
@@ -950,21 +1103,31 @@ def scoreboard_sim(dut, alusim):
 
         # create some instructions (some random, some regression tests)
         instrs = []
-        if True:
-            instrs = create_random_ops(dut, 15, True, 3)
+        if False:
+            instrs = create_random_ops(dut, 15, True, 4)
+
+        if True: # LD test (with immediate)
+            instrs.append( (1, 2, 2, 0x10, 1, 20, (0, 0)) )
+
+        if False:
+            instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )
 
         if False:
             instrs.append( (7, 3, 2, 4, (0, 0)) )
             instrs.append( (7, 6, 6, 2, (0, 0)) )
             instrs.append( (1, 7, 2, 2, (0, 0)) )
 
+        if False:
+            instrs.append((2, 3, 3, 0, 0, 0, (0, 0)))
+            instrs.append((5, 3, 3, 1, 0, 0, (0, 0)))
+            instrs.append((3, 5, 5, 2, 0, 0, (0, 0)))
+            instrs.append((5, 3, 3, 3, 0, 0, (0, 0)))
+            instrs.append((3, 5, 5, 0, 0, 0, (0, 0)))
 
         if False:
-            instrs.append((2, 3, 3, 0, (0, 0)))
-            instrs.append((5, 3, 3, 1, (0, 0)))
-            instrs.append((3, 5, 5, 2, (0, 0)))
-            instrs.append((5, 3, 3, 3, (0, 0)))
-            instrs.append((3, 5, 5, 0, (0, 0)))
+            instrs.append( (3, 3, 4, 0, 0, 13979, (0, 0)))
+            instrs.append( (6, 4, 1, 2, 0, 40976, (0, 0)))
+            instrs.append( (1, 4, 7, 4, 1, 23652, (0, 0)))
 
         if False:
             instrs.append((5, 6, 2, 1))
@@ -1034,22 +1197,25 @@ def scoreboard_sim(dut, alusim):
             instrs.append((4, 2, 1, 2, (1, 0)))
 
         if False:
-            instrs.append( (4, 3, 5, 1, (0, 0)) )
-            instrs.append( (5, 2, 3, 1, (0, 0)) )
-            instrs.append( (7, 1, 5, 2, (0, 0)) )
-            instrs.append( (5, 6, 6, 4, (0, 0)) )
-            instrs.append( (7, 5, 2, 2, (1, 0)) )
-            instrs.append( (1, 7, 5, 0, (0, 1)) )
-            instrs.append( (1, 6, 1, 2, (1, 0)) )
-            instrs.append( (1, 6, 7, 3, (0, 0)) )
-            instrs.append( (6, 7, 7, 0, (0, 0)) )
+            instrs.append( (4, 3, 5, 1, 0, (0, 0)) )
+            instrs.append( (5, 2, 3, 1, 0, (0, 0)) )
+            instrs.append( (7, 1, 5, 2, 0, (0, 0)) )
+            instrs.append( (5, 6, 6, 4, 0, (0, 0)) )
+            instrs.append( (7, 5, 2, 2, 0, (1, 0)) )
+            instrs.append( (1, 7, 5, 0, 0, (0, 1)) )
+            instrs.append( (1, 6, 1, 2, 0, (1, 0)) )
+            instrs.append( (1, 6, 7, 3, 0, (0, 0)) )
+            instrs.append( (6, 7, 7, 0, 0, (0, 0)) )
 
         # issue instruction(s), wait for issue to be free before proceeding
-        for i, (src1, src2, dest, op, (br_ok, br_fail)) in enumerate(instrs):
+        for i, instr in enumerate(instrs):
+            src1, src2, dest, op, opi, imm, (br_ok, br_fail) = instr
 
-            print ("instr %d: (%d, %d, %d, %d)" % (i, src1, src2, dest, op))
-            alusim.op(op, src1, src2, dest)
-            yield from instr_q(dut, op, src1, src2, dest, br_ok, br_fail)
+            print ("instr %d: (%d, %d, %d, %d, %d, %d)" % \
+                    (i, src1, src2, dest, op, opi, imm))
+            alusim.op(op, opi, imm, src1, src2, dest)
+            yield from instr_q(dut, op, opi, imm, src1, src2, dest,
+                               br_ok, br_fail)
 
         # wait for all instructions to stop before checking
         while True:
@@ -1071,6 +1237,7 @@ def scoreboard_sim(dut, alusim):
 def test_scoreboard():
     dut = IssueToScoreboard(2, 1, 1, 16, 8, 8)
     alusim = RegSim(16, 8)
+    memsim = MemSim(16, 16)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_scoreboard6600.il", "w") as f:
         f.write(vl)