X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fscore6600.py;h=ed953e8b71a3b80ff82fde4c93a115d8fcd39303;hb=9160489ce48a008af3e07fdc81d458a0b366f997;hp=e3b4d5778486e252fb5a93d3c98d26c9e9884e5b;hpb=8feb26f6861f891021fdde1e03ecc4d8ee962a05;p=soc.git diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index e3b4d577..ed953e8b 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -202,7 +202,7 @@ class CompUnitsBase(Elaboratable): class CompUnitLDSTs(CompUnitsBase): - def __init__(self, rwid, opwid, mem): + def __init__(self, rwid, opwid, n_ldsts, mem): """ Inputs: * :rwid: bit width of register file(s) - both FP and INT @@ -215,11 +215,12 @@ class CompUnitLDSTs(CompUnitsBase): self.imm_i = Signal(rwid, reset_less=True) # Int ALUs - add1 = ALU(rwid) - add2 = ALU(rwid) + self.alus = [] + for i in range(n_ldsts): + self.alus.append(ALU(rwid)) units = [] - for alu in [add1, add2]: + for alu in self.alus: aluopwid = 4 # see compldst.py for "internal" opcode units.append(LDSTCompUnit(rwid, aluopwid, alu, mem)) @@ -401,13 +402,16 @@ class Scoreboard(Elaboratable): self.fpregs = RegFileArray(rwid, n_regs) # issue q needs to get at these - self.aluissue = IssueUnitGroup(4) + self.aluissue = IssueUnitGroup(2) + self.lsissue = IssueUnitGroup(2) self.brissue = IssueUnitGroup(1) # and these self.alu_oper_i = Signal(4, reset_less=True) self.alu_imm_i = Signal(rwid, reset_less=True) self.br_oper_i = Signal(4, reset_less=True) self.br_imm_i = Signal(rwid, reset_less=True) + self.ls_oper_i = Signal(4, reset_less=True) + self.ls_imm_i = Signal(rwid, reset_less=True) # inputs self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in @@ -446,15 +450,15 @@ class Scoreboard(Elaboratable): # Int ALUs and BR ALUs n_int_alus = 5 - cua = CompUnitALUs(self.rwid, 3, n_alus=4) + cua = CompUnitALUs(self.rwid, 3, n_alus=self.aluissue.n_insns) cub = CompUnitBR(self.rwid, 3) # 1 BR ALUs # LDST Comp Units n_ldsts = 2 - cul = CompUnitLDSTs(self.rwid, 3, None) + cul = CompUnitLDSTs(self.rwid, 4, self.lsissue.n_insns, None) # Comp Units - m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub, cul]) + m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cul, cub]) bgt = cub.bgt # get at the branch computation unit br1 = cub.br1 @@ -475,7 +479,7 @@ class Scoreboard(Elaboratable): # INT/FP Issue Unit regdecode = RegDecode(self.n_regs) m.submodules.regdecode = regdecode - issueunit = IssueUnitArray([self.aluissue, self.brissue]) + issueunit = IssueUnitArray([self.aluissue, self.lsissue, self.brissue]) m.submodules.issueunit = issueunit # Shadow Matrix. currently n_intfus shadows, to be used for @@ -513,6 +517,8 @@ class Scoreboard(Elaboratable): comb += cua.imm_i.eq(self.alu_imm_i) comb += cub.oper_i.eq(self.br_oper_i) comb += cub.imm_i.eq(self.br_imm_i) + comb += cul.oper_i.eq(self.ls_oper_i) + comb += cul.imm_i.eq(self.ls_imm_i) # TODO: issueunit.f (FP) @@ -527,6 +533,19 @@ class Scoreboard(Elaboratable): comb += issueunit.busy_i.eq(cu.busy_o) comb += self.busy_o.eq(cu.busy_o.bool()) + #--------- + # Memory Function Unit + #--------- + comb += memfus.fn_issue_i.eq(cul.issue_i) # Comp Unit Issue -> Mem FUs + comb += memfus.addr_we_i.eq(cul.adr_rel_o) # Match enable on adr rel + + comb += memfus.addrs_i[0].eq(cul.units[0].data_o) + comb += memfus.addrs_i[1].eq(cul.units[1].data_o) + + #comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus]) + #comb += cu.go_wr_i[0:n_intfus].eq(go_wr_o[0:n_intfus]) + #comb += cu.issue_i[0:n_intfus].eq(fn_issue_o[0:n_intfus]) + #--------- # merge shadow matrices outputs #--------- @@ -618,9 +637,9 @@ class Scoreboard(Elaboratable): with m.If(br1.issue_i): sync += bspec.active_i.eq(1) with m.If(self.branch_succ_i): - comb += bspec.good_i.eq(fn_issue_o & 0x1f) + comb += bspec.good_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT with m.If(self.branch_fail_i): - comb += bspec.fail_i.eq(fn_issue_o & 0x1f) + comb += bspec.fail_i.eq(fn_issue_o & 0x1f) # XXX MAGIC CONSTANT # branch is active (TODO: a better signal: this is over-using the # go_write signal - actually the branch should not be "writing") @@ -720,9 +739,13 @@ class IssueToScoreboard(Elaboratable): # in "waiting" state wait_issue_br = Signal() wait_issue_alu = Signal() + wait_issue_ls = Signal() - with m.If(wait_issue_br | wait_issue_alu): + with m.If(wait_issue_br | wait_issue_alu | wait_issue_ls): # set instruction pop length to 1 if the unit accepted + with m.If(wait_issue_ls & (sc.lsissue.fn_issue_o != 0)): + with m.If(iq.qlen_o != 0): + comb += iq.n_sub_i.eq(1) with m.If(wait_issue_br & (sc.brissue.fn_issue_o != 0)): with m.If(iq.qlen_o != 0): comb += iq.n_sub_i.eq(1) @@ -751,14 +774,24 @@ class IssueToScoreboard(Elaboratable): # choose a Function-Unit-Group with m.If((op & (0x3<<2)) != 0): # branch - comb += sc.brissue.insn_i.eq(1) comb += sc.br_oper_i.eq(Cat(op[0:2], opi)) comb += sc.br_imm_i.eq(imm) + comb += sc.brissue.insn_i.eq(1) comb += wait_issue_br.eq(1) - with m.Else(): # alu - comb += sc.aluissue.insn_i.eq(1) + with m.Elif((op & (0x3<<4)) != 0): # ld/st + # see compldst.py + # bit 0: ADD/SUB + # bit 1: immed + # bit 4: LD + # bit 5: ST + comb += sc.ls_oper_i.eq(Cat(op[0], opi[0], op[4:6])) + comb += sc.ls_imm_i.eq(imm) + comb += sc.lsissue.insn_i.eq(1) + comb += wait_issue_ls.eq(1) + with m.Else(): # alu comb += sc.alu_oper_i.eq(Cat(op[0:2], opi)) comb += sc.alu_imm_i.eq(imm) + comb += sc.aluissue.insn_i.eq(1) comb += wait_issue_alu.eq(1) # XXX TODO @@ -789,6 +822,7 @@ IBLT = 5 IBEQ = 6 IBNE = 7 + class RegSim: def __init__(self, rwidth, nregs): self.rwidth = rwidth @@ -817,6 +851,8 @@ class RegSim: val = int(src1 == src2) elif op == IBNE: val = int(src1 != src2) + else: + return 0 # LD/ST TODO val &= maxbits self.setval(dest, val) return val @@ -922,6 +958,7 @@ def wait_for_busy_clear(dut): def disable_issue(dut): yield dut.aluissue.insn_i.eq(0) yield dut.brissue.insn_i.eq(0) + yield dut.lsissue.insn_i.eq(0) def wait_for_issue(dut, dut_issue): @@ -1066,9 +1103,12 @@ def scoreboard_sim(dut, alusim): # create some instructions (some random, some regression tests) instrs = [] - if True: + if False: instrs = create_random_ops(dut, 15, True, 4) + if True: # LD test (with immediate) + instrs.append( (1, 2, 2, 0x10, 1, 20, (0, 0)) ) + if False: instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )