X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpadd%2Fstatemachine.py;h=decbc3d4e87f58630df8afe797d03398a186e857;hb=1464aba03659adec485de985b4b3ebcfc02ba487;hp=4c1365441b0c509c1b8ee07521f5c608f014ee6a;hpb=ccc9261a02d46a5d86836fd43a53882efdab1b82;p=ieee754fpu.git

diff --git a/src/ieee754/fpadd/statemachine.py b/src/ieee754/fpadd/statemachine.py
index 4c136544..decbc3d4 100644
--- a/src/ieee754/fpadd/statemachine.py
+++ b/src/ieee754/fpadd/statemachine.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
@@ -33,20 +33,20 @@ class FPOpData:
     def __init__(self, width, id_wid):
         self.z = FPOpOut(width)
         self.z.data_o = Signal(width)
-        self.mid = Signal(id_wid, reset_less=True)
+        self.muxid = Signal(id_wid, reset_less=True)
 
     def __iter__(self):
         yield self.z
-        yield self.mid
+        yield self.muxid
 
     def eq(self, i):
-        return [self.z.eq(i.z), self.mid.eq(i.mid)]
+        return [self.z.eq(i.z), self.muxid.eq(i.mid)]
 
     def ports(self):
         return list(self)
 
 
-class FPADDBaseMod:
+class FPADDBaseMod(Elaboratable):
 
     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
         """ IEEE754 FP Add
@@ -161,7 +161,7 @@ class FPADDBaseMod:
         get.trigger_setup(m, self.in_t.stb, self.in_t.ack)
 
         chainlist = [get, sc, alm, n1]
-        chain = StageChain(chainlist, specallocate=True)
+        chain = StageChain(chainlist, specallocate=False)
         chain.setup(m, self.i)
         m.submodules.sc = sc
         m.submodules.alm = alm
@@ -268,7 +268,7 @@ class FPADDBase(FPState):
                 m.d.sync += self.out_z.stb.eq(1)
 
 
-class FPADD(FPID):
+class FPADD(FPID, Elaboratable):
     """ FPADD: stages as follows:
 
         FPGetOp (a)