X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpcommon%2Fgetop.py;h=5ca46bfdc281464d0d1a8e220b8c68694d6b166e;hb=1464aba03659adec485de985b4b3ebcfc02ba487;hp=38eb937771259597679324ec8855efd73df382c8;hpb=7ea5658c23398f935ce554766481eb1f28e4f0db;p=ieee754fpu.git

diff --git a/src/ieee754/fpcommon/getop.py b/src/ieee754/fpcommon/getop.py
index 38eb9377..5ca46bfd 100644
--- a/src/ieee754/fpcommon/getop.py
+++ b/src/ieee754/fpcommon/getop.py
@@ -73,33 +73,72 @@ class FPNumBase2Ops:
     def __init__(self, width, id_wid, m_extra=True):
         self.a = FPNumBase(width, m_extra)
         self.b = FPNumBase(width, m_extra)
-        self.mid = Signal(id_wid, reset_less=True)
+        self.muxid = Signal(id_wid, reset_less=True)
 
     def eq(self, i):
-        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+        return [self.a.eq(i.a), self.b.eq(i.b), self.muxid.eq(i.muxid)]
 
     def ports(self):
-        return [self.a, self.b, self.mid]
+        return [self.a, self.b, self.muxid]
+
+
+class FPBaseData:
+
+    def __init__(self, width, pspec):
+        self.width = width
+        print (pspec)
+        self.id_wid = pspec['id_wid']
+        self.op_wid = pspec.get('op_wid', 0)
+        self.muxid = Signal(self.id_wid, reset_less=True)   # RS multiplex ID
+        self.op = Signal(self.op_wid, reset_less=True)
+
+    def eq(self, i):
+        ret = [self.muxid.eq(i.muxid)]
+        if self.op_wid:
+            ret.append(self.op.eq(i.op))
+        return ret
+
+    def __iter__(self):
+        yield self.muxid
+        if self.op_wid:
+            yield self.op
+
+    def ports(self):
+        return list(self)
 
 
 class FPADDBaseData:
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, pspec, n_ops=2):
         self.width = width
-        self.id_wid = id_wid
-        self.a  = Signal(width)                      # operand a
-        self.b  = Signal(width)                      # operand b
-        self.mid = Signal(id_wid, reset_less=True)   # RS multiplex ID
+        self.ctx = FPBaseData(width, pspec)
+        ops = []
+        for i in range(n_ops):
+            name = chr(ord("a")+i)
+            operand = Signal(width, name=name)
+            setattr(self, name, operand)
+            ops.append(operand)
+        self.muxid = self.ctx.muxid # make muxid available here: complicated
+        self.ops = ops
 
     def eq(self, i):
-        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+        ret = []
+        for op1, op2 in zip(self.ops, i.ops):
+            ret.append(op1.eq(op2))
+        ret.append(self.ctx.eq(i.ctx))
+        return ret
+
+    def __iter__(self):
+        if self.ops:
+            yield from self.ops
+        yield from self.ctx
 
     def ports(self):
-        return [self.a, self.b, self.mid]
+        return list(self)
 
 
 class FPGet2OpMod(PrevControl):
-    def __init__(self, width, id_wid):
+    def __init__(self, width, id_wid, op_wid=None):
         PrevControl.__init__(self)
         self.width = width
         self.id_wid = id_wid
@@ -108,10 +147,10 @@ class FPGet2OpMod(PrevControl):
         self.o = self.ospec()
 
     def ispec(self):
-        return FPADDBaseData(self.width, self.id_wid)
+        return FPADDBaseData(self.width, self.id_wid, self.op_wid)
 
     def ospec(self):
-        return FPADDBaseData(self.width, self.id_wid)
+        return FPADDBaseData(self.width, self.id_wid, self.op_wid)
 
     def process(self, i):
         return self.o
@@ -129,10 +168,10 @@ class FPGet2Op(FPState):
     """ gets operands
     """
 
-    def __init__(self, in_state, out_state, width, id_wid):
+    def __init__(self, in_state, out_state, width, id_wid, op_wid=None):
         FPState.__init__(self, in_state)
         self.out_state = out_state
-        self.mod = FPGet2OpMod(width, id_wid)
+        self.mod = FPGet2OpMod(width, id_wid, op_wid)
         self.o = self.ospec()
         self.in_stb = Signal(reset_less=True)
         self.out_ack = Signal(reset_less=True)