X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpcommon%2Froundz.py;h=88795fbe3adab2e4653547ac6d45a1cfd6937d2c;hb=2549b629f84a93f95a6e902e05ea124b6b8a5ad8;hp=3a656459afece9735f0aa78e926f6661d0bfe104;hpb=a7e33cfb272906322f0d677aeb7c6bff4838afeb;p=ieee754fpu.git

diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py
index 3a656459..88795fbe 100644
--- a/src/ieee754/fpcommon/roundz.py
+++ b/src/ieee754/fpcommon/roundz.py
@@ -2,13 +2,13 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Elaboratable
+from nmigen import Module, Signal, Mux
 from nmigen.cli import main, verilog
 
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
-from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.getop import FPPipeContext
-from .postnormalise import FPNorm1Data
+from ieee754.fpcommon.postnormalise import FPNorm1Data
 
 
 class FPRoundData:
@@ -28,12 +28,10 @@ class FPRoundData:
         return ret
 
 
-class FPRoundMod(Elaboratable):
+class FPRoundMod(PipeModBase):
 
     def __init__(self, pspec):
-        self.pspec = pspec
-        self.i = self.ispec()
-        self.out_z = self.ospec()
+        super().__init__(pspec, "roundz")
 
     def ispec(self):
         return FPNorm1Data(self.pspec)
@@ -41,47 +39,16 @@ class FPRoundMod(Elaboratable):
     def ospec(self):
         return FPRoundData(self.pspec)
 
-    def process(self, i):
-        return self.out_z
-
-    def setup(self, m, i):
-        m.submodules.roundz = self
-        m.d.comb += self.i.eq(i)
-
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.out_z.eq(self.i)  # copies muxid, z, out_do_z
-        with m.If(~self.i.out_do_z):  # bypass wasn't enabled
-            with m.If(self.i.roundz):
-                m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1)  # mantissa up
-                with m.If(self.i.z.m == self.i.z.m1s):  # all 1s
-                    # exponent up
-                    m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1)
-
-        return m
+        comb = m.d.comb
 
+        comb += self.o.eq(self.i)  # copies muxid, z, out_do_z
+        im = self.i.z.m
+        ie = self.i.z.e
+        msb1s = Signal(reset_less=True)
+        comb += msb1s.eq(~(~self.i.z.m).bool())  # all 1s
+        comb += self.o.z.m.eq(Mux(self.i.roundz, im+1, im))  # mantissa up
+        comb += self.o.z.e.eq(Mux(msb1s & self.i.roundz, ie + 1, ie)) # exp up
 
-class FPRound(FPState):
-
-    def __init__(self, width, id_wid):
-        FPState.__init__(self, "round")
-        self.mod = FPRoundMod(width)
-        self.out_z = self.ospec()
-
-    def ispec(self):
-        return self.mod.ispec()
-
-    def ospec(self):
-        return self.mod.ospec()
-
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        self.mod.setup(m, i)
-
-        self.idsync(m)
-        m.d.sync += self.out_z.eq(self.mod.out_z)
-        m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)
-
-    def action(self, m):
-        m.next = "corrections"
+        return m