X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpcommon%2Froundz.py;h=88795fbe3adab2e4653547ac6d45a1cfd6937d2c;hb=2549b629f84a93f95a6e902e05ea124b6b8a5ad8;hp=a4077cfdd843f26df13761f203364b17c2db7b70;hpb=092e76403be53ff1cbcb7bef05dbdd3304c8927a;p=ieee754fpu.git

diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py
index a4077cfd..88795fbe 100644
--- a/src/ieee754/fpcommon/roundz.py
+++ b/src/ieee754/fpcommon/roundz.py
@@ -2,10 +2,10 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Mux
 from nmigen.cli import main, verilog
 
-from ieee754.fpcommon.modbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
 from ieee754.fpcommon.getop import FPPipeContext
 from ieee754.fpcommon.postnormalise import FPNorm1Data
@@ -28,7 +28,7 @@ class FPRoundData:
         return ret
 
 
-class FPRoundMod(FPModBase):
+class FPRoundMod(PipeModBase):
 
     def __init__(self, pspec):
         super().__init__(pspec, "roundz")
@@ -44,11 +44,11 @@ class FPRoundMod(FPModBase):
         comb = m.d.comb
 
         comb += self.o.eq(self.i)  # copies muxid, z, out_do_z
-        with m.If(~self.i.out_do_z):  # bypass wasn't enabled
-            with m.If(self.i.roundz):
-                comb += self.o.z.m.eq(self.i.z.m + 1)  # mantissa up
-                with m.If(self.i.z.m == self.i.z.m1s):  # all 1s
-                    # exponent up
-                    comb += self.o.z.e.eq(self.i.z.e + 1)
+        im = self.i.z.m
+        ie = self.i.z.e
+        msb1s = Signal(reset_less=True)
+        comb += msb1s.eq(~(~self.i.z.m).bool())  # all 1s
+        comb += self.o.z.m.eq(Mux(self.i.roundz, im+1, im))  # mantissa up
+        comb += self.o.z.e.eq(Mux(msb1s & self.i.roundz, ie + 1, ie)) # exp up
 
         return m