X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpcommon%2Froundz.py;h=ceec0c463a51d5e622f92a2f4643974b695f2e8a;hb=1464aba03659adec485de985b4b3ebcfc02ba487;hp=2b456fba47988865b580fde16c06ce02f4120909;hpb=da918b3777224f5fe562d23eebc3b110261a8c8f;p=ieee754fpu.git

diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py
index 2b456fba..ceec0c46 100644
--- a/src/ieee754/fpcommon/roundz.py
+++ b/src/ieee754/fpcommon/roundz.py
@@ -5,37 +5,41 @@
 from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumBase
-from fpbase import FPState
+from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
+from ieee754.fpcommon.fpbase import FPState
+from ieee754.fpcommon.getop import FPBaseData
 from .postnormalise import FPNorm1Data
 
 
 class FPRoundData:
 
-    def __init__(self, width, id_wid):
-        self.z = FPNumBase(width, False)
+    def __init__(self, width, pspec):
+        self.z = FPNumBaseRecord(width, False)
+        self.ctx = FPBaseData(width, pspec)
+        self.muxid = self.ctx.muxid
+        # pipeline bypass [data comes from specialcases]
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
-        self.mid = Signal(id_wid, reset_less=True)
 
     def eq(self, i):
-        return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-                self.mid.eq(i.mid)]
+        ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+                self.ctx.eq(i.ctx)]
+        return ret
 
 
 class FPRoundMod(Elaboratable):
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, pspec):
         self.width = width
-        self.id_wid = id_wid
+        self.pspec = pspec
         self.i = self.ispec()
         self.out_z = self.ospec()
 
     def ispec(self):
-        return FPNorm1Data(self.width, self.id_wid)
+        return FPNorm1Data(self.width, self.pspec)
 
     def ospec(self):
-        return FPRoundData(self.width, self.id_wid)
+        return FPRoundData(self.width, self.pspec)
 
     def process(self, i):
         return self.out_z
@@ -47,7 +51,7 @@ class FPRoundMod(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
-        with m.If(~self.i.out_do_z):
+        with m.If(~self.i.out_do_z): # bypass wasn't enabled
             with m.If(self.i.roundz):
                 m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
                 with m.If(self.i.z.m == self.i.z.m1s): # all 1s
@@ -76,7 +80,7 @@ class FPRound(FPState):
 
         self.idsync(m)
         m.d.sync += self.out_z.eq(self.mod.out_z)
-        m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
+        m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)
 
     def action(self, m):
         m.next = "corrections"