X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpcommon%2Froundz.py;h=ceec0c463a51d5e622f92a2f4643974b695f2e8a;hb=1464aba03659adec485de985b4b3ebcfc02ba487;hp=dd65551022f307af249a06de9d9090cdccb30ede;hpb=a7d0eedd5131906af7e63ea8f64f8a49b827bb48;p=ieee754fpu.git diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py index dd655510..ceec0c46 100644 --- a/src/ieee754/fpcommon/roundz.py +++ b/src/ieee754/fpcommon/roundz.py @@ -7,44 +7,39 @@ from nmigen.cli import main, verilog from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord from ieee754.fpcommon.fpbase import FPState +from ieee754.fpcommon.getop import FPBaseData from .postnormalise import FPNorm1Data class FPRoundData: - def __init__(self, width, id_wid, op_wid=None): + def __init__(self, width, pspec): self.z = FPNumBaseRecord(width, False) - self.mid = Signal(id_wid, reset_less=True) # multiplex ID + self.ctx = FPBaseData(width, pspec) + self.muxid = self.ctx.muxid # pipeline bypass [data comes from specialcases] self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) - self.op_wid = op_wid - if op_wid: - self.op = Signal(op_wid, reset_less=True) def eq(self, i): ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), - self.mid.eq(i.mid)] - if self.op_wid: - ret.append(self.op.eq(i.op)) + self.ctx.eq(i.ctx)] return ret - class FPRoundMod(Elaboratable): - def __init__(self, width, id_wid, op_wid=None): + def __init__(self, width, pspec): self.width = width - self.id_wid = id_wid - self.op_wid = op_wid + self.pspec = pspec self.i = self.ispec() self.out_z = self.ospec() def ispec(self): - return FPNorm1Data(self.width, self.id_wid, self.op_wid) + return FPNorm1Data(self.width, self.pspec) def ospec(self): - return FPRoundData(self.width, self.id_wid, self.op_wid) + return FPRoundData(self.width, self.pspec) def process(self, i): return self.out_z @@ -85,7 +80,7 @@ class FPRound(FPState): self.idsync(m) m.d.sync += self.out_z.eq(self.mod.out_z) - m.d.sync += self.out_z.mid.eq(self.mod.o.mid) + m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx) def action(self, m): m.next = "corrections"