X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpdiv%2Fdiv0.py;h=fb2bccd6302ad0a7688c6378194550a5ffdeb2f5;hb=47db0fc7fe59d4a9cf356ee0caf7c3ce143f8683;hp=796e6c29c09bd835dae1f396daa2cd597900fe88;hpb=9242ee2c8f892d95ac15b09fc260f820f127ec8d;p=ieee754fpu.git

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 796e6c29..fb2bccd6 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -6,29 +6,32 @@ Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
 from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
 
-from ieee754.fpcommon.fpbase import FPNumBaseRecord
+from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.getop import FPPipeContext
 
 
+# TODO: delete (replace by DivPipeCoreInputData)
 class FPDivStage0Data:
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, pspec):
         self.z = FPNumBaseRecord(width, False)
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
 
+        self.ctx = FPPipeContext(width, pspec) # context: muxid, operator etc.
+        self.muxid = self.ctx.muxid             # annoying. complicated.
+
         # TODO: here is where Q and R would be put, and passed
         # down to Stage1 processing.
 
         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         self.product = Signal(mw, reset_less=True)
 
-        self.mid = Signal(id_wid, reset_less=True)
-
     def eq(self, i):
         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-                self.product.eq(i.product), self.mid.eq(i.mid)]
+                self.product.eq(i.product), self.ctx.eq(i.ctx)]
 
 
 class FPDivStage0Mod(Elaboratable):
@@ -43,6 +46,7 @@ class FPDivStage0Mod(Elaboratable):
         return FPSCData(self.width, self.id_wid, False)
 
     def ospec(self):
+        # XXX TODO: replace with DivPipeCoreInputData, here
         return FPDivStage0Data(self.width, self.id_wid)
 
     def process(self, i):
@@ -58,10 +62,18 @@ class FPDivStage0Mod(Elaboratable):
         m = Module()
 
         # XXX TODO, actual DIV code here.  this class would be
-        # "step one" which takes the pre-normalised data and
+        # "step one" which takes the pre-normalised data (see ispec) and
         # *begins* the processing phase (enters the massive DIV
-        # pipeline chain)
+        # pipeline chain) - see ospec.
+
+        # INPUT SPEC: FPSCData
+        # OUTPUT SPEC: DivPipeCoreInputData
 
+        # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
+        # it is PURELY the *ENTRY* point into the chain, performing
+        # "preparation" work.
+
+        # delete this
         # store intermediate tests (and zero-extended mantissas)
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
@@ -69,8 +81,11 @@ class FPDivStage0Mod(Elaboratable):
                      am0.eq(Cat(self.i.a.m, 0)),
                      bm0.eq(Cat(self.i.b.m, 0))
                     ]
-        # same-sign (both negative or both positive) div mantissas
+
         with m.If(~self.i.out_do_z):
+            # do conversion here, of both self.i.a and self.i.b,
+            # into DivPipeCoreInputData dividend and divisor.
+
             m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
                          # TODO: no, not product, first stage Q and R etc. etc.
                          # go here.
@@ -78,9 +93,11 @@ class FPDivStage0Mod(Elaboratable):
                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
                 ]
 
+        # these are required and must not be touched
         m.d.comb += self.o.oz.eq(self.i.oz)
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
-        m.d.comb += self.o.mid.eq(self.i.mid)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
+
         return m