X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Fpart_mul_add%2Fmultiply.py;h=4c6b570ce4474008c4fc590110afb1719cb818cb;hb=92ca6002d7435795ef3e20c8be00567786baec5d;hp=dbb09d03808c00a1ee6095d600bddf346c635b34;hpb=9662e1b65a20183d1f9a0c9dbb9acd98b63c6cb8;p=ieee754fpu.git diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py index dbb09d03..4c6b570c 100644 --- a/src/ieee754/part_mul_add/multiply.py +++ b/src/ieee754/part_mul_add/multiply.py @@ -346,19 +346,25 @@ class FinalAdd(Elaboratable): """ Final stage of add reduce """ - def __init__(self, n_inputs, output_width, n_parts, register_levels, - partition_points): - self.i = AddReduceData(partition_points, n_inputs, - output_width, n_parts) - self.o = FinalReduceData(partition_points, output_width, n_parts) + def __init__(self, n_inputs, output_width, n_parts, partition_points): self.output_width = output_width self.n_inputs = n_inputs self.n_parts = n_parts - self.register_levels = list(register_levels) self.partition_points = PartitionPoints(partition_points) if not self.partition_points.fits_in_width(output_width): raise ValueError("partition_points doesn't fit in output_width") + self.i = self.ispec() + self.o = self.ospec() + + def ispec(self): + return AddReduceData(self.partition_points, self.n_inputs, + self.output_width, self.n_parts) + + def ospec(self): + return FinalReduceData(self.partition_points, + self.output_width, self.n_parts) + def elaborate(self, platform): """Elaborate this module.""" m = Module() @@ -400,35 +406,33 @@ class AddReduceSingle(Elaboratable): supported, except for by ``Signal.eq``. """ - def __init__(self, n_inputs, output_width, n_parts, register_levels, - partition_points): + def __init__(self, n_inputs, output_width, n_parts, partition_points): """Create an ``AddReduce``. :param inputs: input ``Signal``s to be summed. :param output_width: bit-width of ``output``. - :param register_levels: List of nesting levels that should have - pipeline registers. :param partition_points: the input partition points. """ self.n_inputs = n_inputs self.n_parts = n_parts self.output_width = output_width - self.i = AddReduceData(partition_points, n_inputs, - output_width, n_parts) - self.register_levels = list(register_levels) self.partition_points = PartitionPoints(partition_points) if not self.partition_points.fits_in_width(output_width): raise ValueError("partition_points doesn't fit in output_width") - max_level = AddReduceSingle.get_max_level(n_inputs) - for level in self.register_levels: - if level > max_level: - raise ValueError( - "not enough adder levels for specified register levels") - self.groups = AddReduceSingle.full_adder_groups(n_inputs) - n_terms = AddReduceSingle.calc_n_inputs(n_inputs, self.groups) - self.o = AddReduceData(partition_points, n_terms, output_width, n_parts) + self.n_terms = AddReduceSingle.calc_n_inputs(n_inputs, self.groups) + + self.i = self.ispec() + self.o = self.ospec() + + def ispec(self): + return AddReduceData(self.partition_points, self.n_inputs, + self.output_width, self.n_parts) + + def ospec(self): + return AddReduceData(self.partition_points, self.n_terms, + self.output_width, self.n_parts) @staticmethod def calc_n_inputs(n_inputs, groups): @@ -527,7 +531,7 @@ class AddReduceSingle(Elaboratable): return m -class AddReduce(Elaboratable): +class AddReduceInternal: """Recursively Add list of numbers together. :attribute inputs: input ``Signal``s to be summed. Modification not @@ -539,42 +543,25 @@ class AddReduce(Elaboratable): supported, except for by ``Signal.eq``. """ - def __init__(self, inputs, output_width, register_levels, partition_points, - part_ops): + def __init__(self, i, output_width): """Create an ``AddReduce``. :param inputs: input ``Signal``s to be summed. :param output_width: bit-width of ``output``. - :param register_levels: List of nesting levels that should have - pipeline registers. :param partition_points: the input partition points. """ - self.inputs = inputs - self.part_ops = part_ops - n_parts = len(part_ops) - self.o = FinalReduceData(partition_points, output_width, n_parts) + self.i = i + self.inputs = i.terms + self.part_ops = i.part_ops self.output_width = output_width - self.register_levels = register_levels - self.partition_points = partition_points + self.partition_points = i.part_pts self.create_levels() - @staticmethod - def get_max_level(input_count): - return AddReduceSingle.get_max_level(input_count) - - @staticmethod - def next_register_levels(register_levels): - """``Iterable`` of ``register_levels`` for next recursive level.""" - for level in register_levels: - if level > 0: - yield level - 1 - def create_levels(self): """creates reduction levels""" mods = [] - next_levels = self.register_levels partition_points = self.partition_points part_ops = self.part_ops n_parts = len(part_ops) @@ -585,38 +572,76 @@ class AddReduce(Elaboratable): if len(groups) == 0: break next_level = AddReduceSingle(ilen, self.output_width, n_parts, - next_levels, partition_points) + partition_points) mods.append(next_level) - next_levels = list(AddReduce.next_register_levels(next_levels)) partition_points = next_level.i.part_pts inputs = next_level.o.terms ilen = len(inputs) part_ops = next_level.i.part_ops next_level = FinalAdd(ilen, self.output_width, n_parts, - next_levels, partition_points) + partition_points) mods.append(next_level) self.levels = mods + +class AddReduce(AddReduceInternal, Elaboratable): + """Recursively Add list of numbers together. + + :attribute inputs: input ``Signal``s to be summed. Modification not + supported, except for by ``Signal.eq``. + :attribute register_levels: List of nesting levels that should have + pipeline registers. + :attribute output: output sum. + :attribute partition_points: the input partition points. Modification not + supported, except for by ``Signal.eq``. + """ + + def __init__(self, inputs, output_width, register_levels, part_pts, + part_ops): + """Create an ``AddReduce``. + + :param inputs: input ``Signal``s to be summed. + :param output_width: bit-width of ``output``. + :param register_levels: List of nesting levels that should have + pipeline registers. + :param partition_points: the input partition points. + """ + self._inputs = inputs + self._part_pts = part_pts + self._part_ops = part_ops + n_parts = len(part_ops) + self.i = AddReduceData(part_pts, len(inputs), + output_width, n_parts) + AddReduceInternal.__init__(self, self.i, output_width) + self.o = FinalReduceData(part_pts, output_width, n_parts) + self.register_levels = register_levels + + @staticmethod + def get_max_level(input_count): + return AddReduceSingle.get_max_level(input_count) + + @staticmethod + def next_register_levels(register_levels): + """``Iterable`` of ``register_levels`` for next recursive level.""" + for level in register_levels: + if level > 0: + yield level - 1 + def elaborate(self, platform): """Elaborate this module.""" m = Module() + m.d.comb += self.i.eq_from(self._part_pts, self._inputs, self._part_ops) + for i, next_level in enumerate(self.levels): setattr(m.submodules, "next_level%d" % i, next_level) - partition_points = self.partition_points - inputs = self.inputs - part_ops = self.part_ops - n_parts = len(part_ops) - n_inputs = len(inputs) - output_width = self.output_width - i = AddReduceData(partition_points, n_inputs, output_width, n_parts) - m.d.comb += i.eq_from(partition_points, inputs, part_ops) + i = self.i for idx in range(len(self.levels)): mcur = self.levels[idx] - if 0 in mcur.register_levels: + if idx in self.register_levels: m.d.sync += mcur.i.eq(i) else: m.d.comb += mcur.i.eq(i) @@ -689,8 +714,8 @@ class ProductTerm(Elaboratable): bsb = Signal(self.width, reset_less=True) a_index, b_index = self.a_index, self.b_index pwidth = self.pwidth - m.d.comb += bsa.eq(self.a.part(a_index * pwidth, pwidth)) - m.d.comb += bsb.eq(self.b.part(b_index * pwidth, pwidth)) + m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth)) + m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth)) m.d.comb += self.ti.eq(bsa * bsb) m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled)) """ @@ -704,8 +729,8 @@ class ProductTerm(Elaboratable): asel = Signal(width, reset_less=True) bsel = Signal(width, reset_less=True) a_index, b_index = self.a_index, self.b_index - m.d.comb += asel.eq(self.a.part(a_index * pwidth, pwidth)) - m.d.comb += bsel.eq(self.b.part(b_index * pwidth, pwidth)) + m.d.comb += asel.eq(self.a.bit_select(a_index * pwidth, pwidth)) + m.d.comb += bsel.eq(self.b.bit_select(b_index * pwidth, pwidth)) m.d.comb += bsa.eq(get_term(asel, self.shift, self.enabled)) m.d.comb += bsb.eq(get_term(bsel, self.shift, self.enabled)) m.d.comb += self.ti.eq(bsa * bsb) @@ -885,7 +910,7 @@ class Part(Elaboratable): pa = LSBNegTerm(bit_wid) setattr(m.submodules, "lnt_%d_a_%d" % (bit_wid, i), pa) m.d.comb += pa.part.eq(parts[i]) - m.d.comb += pa.op.eq(self.a.part(bit_wid * i, bit_wid)) + m.d.comb += pa.op.eq(self.a.bit_select(bit_wid * i, bit_wid)) m.d.comb += pa.signed.eq(self.b_signed[i * byte_width]) # yes b m.d.comb += pa.msb.eq(self.b[(i + 1) * bit_wid - 1]) # really, b nat.append(pa.nt) @@ -895,7 +920,7 @@ class Part(Elaboratable): pb = LSBNegTerm(bit_wid) setattr(m.submodules, "lnt_%d_b_%d" % (bit_wid, i), pb) m.d.comb += pb.part.eq(parts[i]) - m.d.comb += pb.op.eq(self.b.part(bit_wid * i, bit_wid)) + m.d.comb += pb.op.eq(self.b.bit_select(bit_wid * i, bit_wid)) m.d.comb += pb.signed.eq(self.a_signed[i * byte_width]) # yes a m.d.comb += pb.msb.eq(self.a[(i + 1) * bit_wid - 1]) # really, a nbt.append(pb.nt) @@ -933,8 +958,8 @@ class IntermediateOut(Elaboratable): op = Signal(w, reset_less=True, name="op%d_%d" % (w, i)) m.d.comb += op.eq( Mux(self.part_ops[sel * i] == OP_MUL_LOW, - self.intermed.part(i * w*2, w), - self.intermed.part(i * w*2 + w, w))) + self.intermed.bit_select(i * w*2, w), + self.intermed.bit_select(i * w*2 + w, w))) ol.append(op) m.d.comb += self.output.eq(Cat(*ol)) @@ -950,20 +975,27 @@ class FinalOut(Elaboratable): """ def __init__(self, output_width, n_parts, part_pts): self.part_pts = part_pts - self.i = IntermediateData(part_pts, output_width, n_parts) + self.output_width = output_width + self.n_parts = n_parts self.out_wid = output_width//2 - # output - self.out = Signal(self.out_wid, reset_less=True) - self.intermediate_output = Signal(output_width, reset_less=True) + + self.i = self.ispec() + self.o = self.ospec() + + def ispec(self): + return IntermediateData(self.part_pts, self.output_width, self.n_parts) + + def ospec(self): + return OutputData() def elaborate(self, platform): m = Module() - pps = self.part_pts - m.submodules.p_8 = p_8 = Parts(8, pps, 8) - m.submodules.p_16 = p_16 = Parts(8, pps, 4) - m.submodules.p_32 = p_32 = Parts(8, pps, 2) - m.submodules.p_64 = p_64 = Parts(8, pps, 1) + part_pts = self.part_pts + m.submodules.p_8 = p_8 = Parts(8, part_pts, 8) + m.submodules.p_16 = p_16 = Parts(8, part_pts, 4) + m.submodules.p_32 = p_32 = Parts(8, part_pts, 2) + m.submodules.p_64 = p_64 = Parts(8, part_pts, 1) out_part_pts = self.i.part_pts @@ -1003,11 +1035,16 @@ class FinalOut(Elaboratable): op = Signal(8, reset_less=True, name="op_%d" % i) m.d.comb += op.eq( Mux(d8[i] | d16[i // 2], - Mux(d8[i], i8.part(i * 8, 8), i16.part(i * 8, 8)), - Mux(d32[i // 4], i32.part(i * 8, 8), i64.part(i * 8, 8)))) + Mux(d8[i], i8.bit_select(i * 8, 8), + i16.bit_select(i * 8, 8)), + Mux(d32[i // 4], i32.bit_select(i * 8, 8), + i64.bit_select(i * 8, 8)))) ol.append(op) - m.d.comb += self.out.eq(Cat(*ol)) - m.d.comb += self.intermediate_output.eq(self.i.intermediate_output) + + # create outputs + m.d.comb += self.o.output.eq(Cat(*ol)) + m.d.comb += self.o.intermediate_output.eq(self.i.intermediate_output) + return m @@ -1079,15 +1116,17 @@ class IntermediateData: rhs.intermediate_output, rhs.part_ops) -class AllTermsData: +class InputData: - def __init__(self, partition_points): + def __init__(self): self.a = Signal(64) self.b = Signal(64) - self.part_pts = partition_points.like() + self.part_pts = PartitionPoints() + for i in range(8, 64, 8): + self.part_pts[i] = Signal(name=f"part_pts_{i}") self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)] - def eq_from(self, part_pts, inputs, part_ops): + def eq_from(self, part_pts, a, b, part_ops): return [self.part_pts.eq(part_pts)] + \ [self.a.eq(a), self.b.eq(b)] + \ [self.part_ops[i].eq(part_ops[i]) @@ -1097,12 +1136,22 @@ class AllTermsData: return self.eq_from(rhs.part_pts, rhs.a, rhs.b, rhs.part_ops) +class OutputData: + + def __init__(self): + self.intermediate_output = Signal(128) # needed for unit tests + self.output = Signal(64) + + def eq(self, rhs): + return [self.intermediate_output.eq(rhs.intermediate_output), + self.output.eq(rhs.output)] + + class AllTerms(Elaboratable): """Set of terms to be added together """ - def __init__(self, n_inputs, output_width, n_parts, register_levels, - partition_points): + def __init__(self, n_inputs, output_width, n_parts, register_levels): """Create an ``AddReduce``. :param inputs: input ``Signal``s to be summed. @@ -1111,13 +1160,20 @@ class AllTerms(Elaboratable): pipeline registers. :param partition_points: the input partition points. """ - self.i = AllTermsData(partition_points) self.register_levels = register_levels self.n_inputs = n_inputs self.n_parts = n_parts self.output_width = output_width - self.o = AddReduceData(self.i.part_pts, n_inputs, - output_width, n_parts) + + self.i = self.ispec() + self.o = self.ospec() + + def ispec(self): + return InputData() + + def ospec(self): + return AddReduceData(self.i.part_pts, self.n_inputs, + self.output_width, self.n_parts) def elaborate(self, platform): m = Module() @@ -1202,9 +1258,19 @@ class Intermediates(Elaboratable): """ Intermediate output modules """ - def __init__(self, output_width, n_parts, partition_points): - self.i = FinalReduceData(partition_points, output_width, n_parts) - self.o = IntermediateData(partition_points, output_width, n_parts) + def __init__(self, output_width, n_parts, part_pts): + self.part_pts = part_pts + self.output_width = output_width + self.n_parts = n_parts + + self.i = self.ispec() + self.o = self.ospec() + + def ispec(self): + return FinalReduceData(self.part_pts, self.output_width, self.n_parts) + + def ospec(self): + return IntermediateData(self.part_pts, self.output_width, self.n_parts) def elaborate(self, platform): m = Module() @@ -1284,34 +1350,35 @@ class Mul8_16_32_64(Elaboratable): # parameter(s) self.register_levels = list(register_levels) - # inputs - self.part_pts = PartitionPoints() - for i in range(8, 64, 8): - self.part_pts[i] = Signal(name=f"part_pts_{i}") - self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)] - self.a = Signal(64) - self.b = Signal(64) + self.i = self.ispec() + self.o = self.ospec() - # intermediates (needed for unit tests) - self.intermediate_output = Signal(128) + # inputs + self.part_pts = self.i.part_pts + self.part_ops = self.i.part_ops + self.a = self.i.a + self.b = self.i.b # output - self.output = Signal(64) + self.intermediate_output = self.o.intermediate_output + self.output = self.o.output + + def ispec(self): + return InputData() + + def ospec(self): + return OutputData() def elaborate(self, platform): m = Module() - pps = self.part_pts + part_pts = self.part_pts n_inputs = 64 + 4 - n_parts = 8 #len(self.part_pts) - t = AllTerms(n_inputs, 128, n_parts, self.register_levels, pps) + n_parts = 8 + t = AllTerms(n_inputs, 128, n_parts, self.register_levels) m.submodules.allterms = t - m.d.comb += t.i.a.eq(self.a) - m.d.comb += t.i.b.eq(self.b) - m.d.comb += t.i.part_pts.eq(pps) - for i in range(8): - m.d.comb += t.i.part_ops[i].eq(self.part_ops[i]) + m.d.comb += t.i.eq(self.i) terms = t.o.terms @@ -1321,20 +1388,16 @@ class Mul8_16_32_64(Elaboratable): t.o.part_pts, t.o.part_ops) - out_part_ops = add_reduce.o.part_ops - out_part_pts = add_reduce.o.part_pts - m.submodules.add_reduce = add_reduce - interm = Intermediates(128, 8, pps) + interm = Intermediates(128, 8, part_pts) m.submodules.intermediates = interm m.d.comb += interm.i.eq(add_reduce.o) # final output - m.submodules.finalout = finalout = FinalOut(128, 8, pps) + m.submodules.finalout = finalout = FinalOut(128, 8, part_pts) m.d.comb += finalout.i.eq(interm.o) - m.d.comb += self.output.eq(finalout.out) - m.d.comb += self.intermediate_output.eq(finalout.intermediate_output) + m.d.comb += self.o.eq(finalout.o) return m