X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Fpart_mul_add%2Fmultiply.py;h=6f770842f8aa048c6afc2b8e54b5013f2e91e985;hb=f20d60b428a9e313866a703f68d5b6e638e296c2;hp=2771e882d08c382df70e5523e6d843b0d1027189;hpb=88bb34cd8fb4c6428e26afc6a24351c3e841fd39;p=ieee754fpu.git diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py index 2771e882..6f770842 100644 --- a/src/ieee754/part_mul_add/multiply.py +++ b/src/ieee754/part_mul_add/multiply.py @@ -132,11 +132,11 @@ class FullAdder(Elaboratable): :param width: the bit width of the input and output """ - self.in0 = Signal(width) - self.in1 = Signal(width) - self.in2 = Signal(width) - self.sum = Signal(width) - self.carry = Signal(width) + self.in0 = Signal(width, reset_less=True) + self.in1 = Signal(width, reset_less=True) + self.in2 = Signal(width, reset_less=True) + self.sum = Signal(width, reset_less=True) + self.carry = Signal(width, reset_less=True) def elaborate(self, platform): """Elaborate this module.""" @@ -234,9 +234,9 @@ class PartitionedAdder(Elaboratable): :param partition_points: the input partition points """ self.width = width - self.a = Signal(width) - self.b = Signal(width) - self.output = Signal(width) + self.a = Signal(width, reset_less=True) + self.b = Signal(width, reset_less=True) + self.output = Signal(width, reset_less=True) self.partition_points = PartitionPoints(partition_points) if not self.partition_points.fits_in_width(width): raise ValueError("partition_points doesn't fit in width") @@ -246,17 +246,14 @@ class PartitionedAdder(Elaboratable): expanded_width += 1 expanded_width += 1 self._expanded_width = expanded_width - # XXX these have to remain here due to some horrible nmigen - # simulation bugs involving sync. it is *not* necessary to - # have them here, they should (under normal circumstances) - # be moved into elaborate, as they are entirely local - self._expanded_a = Signal(expanded_width) # includes extra part-points - self._expanded_b = Signal(expanded_width) # likewise. - self._expanded_o = Signal(expanded_width) # likewise. def elaborate(self, platform): """Elaborate this module.""" m = Module() + expanded_a = Signal(self._expanded_width, reset_less=True) + expanded_b = Signal(self._expanded_width, reset_less=True) + expanded_o = Signal(self._expanded_width, reset_less=True) + expanded_index = 0 # store bits in a list, use Cat later. graphviz is much cleaner al, bl, ol, ea, eb, eo = [],[],[],[],[],[] @@ -273,14 +270,14 @@ class PartitionedAdder(Elaboratable): if i in self.partition_points: # add extra bit set to 0 + 0 for enabled partition points # and 1 + 0 for disabled partition points - ea.append(self._expanded_a[expanded_index]) + ea.append(expanded_a[expanded_index]) al.append(~self.partition_points[i]) # add extra bit in a - eb.append(self._expanded_b[expanded_index]) + eb.append(expanded_b[expanded_index]) bl.append(C(0)) # yes, add a zero expanded_index += 1 # skip the extra point. NOT in the output - ea.append(self._expanded_a[expanded_index]) - eb.append(self._expanded_b[expanded_index]) - eo.append(self._expanded_o[expanded_index]) + ea.append(expanded_a[expanded_index]) + eb.append(expanded_b[expanded_index]) + eo.append(expanded_o[expanded_index]) al.append(self.a[i]) bl.append(self.b[i]) ol.append(self.output[i]) @@ -293,8 +290,7 @@ class PartitionedAdder(Elaboratable): # use only one addition to take advantage of look-ahead carry and # special hardware on FPGAs - m.d.comb += self._expanded_o.eq( - self._expanded_a + self._expanded_b) + m.d.comb += expanded_o.eq(expanded_a + expanded_b) return m @@ -303,10 +299,11 @@ FULL_ADDER_INPUT_COUNT = 3 class AddReduceData: def __init__(self, ppoints, n_inputs, output_width, n_parts): - self.part_ops = [Signal(2, name=f"part_ops_{i}") + self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True) for i in range(n_parts)] - self.inputs = [Signal(output_width, name=f"inputs[{i}]") - for i in range(n_inputs)] + self.inputs = [Signal(output_width, name=f"inputs_{i}", + reset_less=True) + for i in range(n_inputs)] self.reg_partition_points = ppoints.like() def eq_from(self, reg_partition_points, inputs, part_ops): @@ -323,9 +320,9 @@ class AddReduceData: class FinalReduceData: def __init__(self, ppoints, output_width, n_parts): - self.part_ops = [Signal(2, name=f"part_ops_{i}") + self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True) for i in range(n_parts)] - self.output = Signal(output_width) + self.output = Signal(output_width, reset_less=True) self.reg_partition_points = ppoints.like() def eq_from(self, reg_partition_points, output, part_ops): @@ -360,7 +357,7 @@ class FinalAdd(Elaboratable): m = Module() output_width = self.output_width - output = Signal(output_width) + output = Signal(output_width, reset_less=True) if self.n_inputs == 0: # use 0 as the default output value m.d.comb += output.eq(0) @@ -427,6 +424,7 @@ class AddReduceSingle(Elaboratable): # etc because this is not in elaboratable. self.groups = AddReduceSingle.full_adder_groups(n_inputs) self._intermediate_terms = [] + self.adders = [] if len(self.groups) != 0: self.create_next_terms() @@ -470,8 +468,10 @@ class AddReduceSingle(Elaboratable): for i in range(len(self.i.part_ops))] # set up the partition mask (for the adders) + part_mask = Signal(self.output_width, reset_less=True) + mask = self.i.reg_partition_points.as_mask(self.output_width) - m.d.comb += self.part_mask.eq(mask) + m.d.comb += part_mask.eq(mask) # add and link the intermediate term modules for i, (iidx, adder_i) in enumerate(self.adders): @@ -480,7 +480,7 @@ class AddReduceSingle(Elaboratable): m.d.comb += adder_i.in0.eq(self.i.inputs[iidx]) m.d.comb += adder_i.in1.eq(self.i.inputs[iidx + 1]) m.d.comb += adder_i.in2.eq(self.i.inputs[iidx + 2]) - m.d.comb += adder_i.mask.eq(self.part_mask) + m.d.comb += adder_i.mask.eq(part_mask) return m @@ -491,12 +491,8 @@ class AddReduceSingle(Elaboratable): def add_intermediate_term(value): _intermediate_terms.append(value) - # store mask in intermediary (simplifies graph) - self.part_mask = Signal(self.output_width, reset_less=True) - # create full adders for this recursive level. # this shrinks N terms to 2 * (N // 3) plus the remainder - self.adders = [] for i in self.groups: adder_i = MaskedFullAdder(self.output_width) self.adders.append((i, adder_i)) @@ -573,6 +569,9 @@ class AddReduce(Elaboratable): inputs = self.inputs ilen = len(inputs) while True: + groups = AddReduceSingle.full_adder_groups(len(inputs)) + if len(groups) == 0: + break next_level = AddReduceSingle(ilen, self.output_width, n_parts, next_levels, partition_points) mods.append(next_level) @@ -581,9 +580,6 @@ class AddReduce(Elaboratable): inputs = next_level.o.inputs ilen = len(inputs) part_ops = next_level.i.part_ops - groups = AddReduceSingle.full_adder_groups(len(inputs)) - if len(groups) == 0: - break next_level = FinalAdd(ilen, self.output_width, n_parts, next_levels, partition_points) @@ -614,7 +610,6 @@ class AddReduce(Elaboratable): m.d.comb += mcur.i.eq(i) i = mcur.o # for next loop - print ("levels", len(self.levels), i) # output comes from last module m.d.comb += self.o.eq(i) @@ -784,7 +779,8 @@ class Parts(Elaboratable): # inputs self.epps = PartitionPoints.like(epps, name="epps") # expanded points # outputs - self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)] + self.parts = [Signal(name=f"part_{i}", reset_less=True) + for i in range(n_parts)] def elaborate(self, platform): m = Module() @@ -837,19 +833,22 @@ class Part(Elaboratable): self.epps = epps # inputs - self.a = Signal(64) - self.b = Signal(64) - self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)] - self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)] + self.a = Signal(64, reset_less=True) + self.b = Signal(64, reset_less=True) + self.a_signed = [Signal(name=f"a_signed_{i}", reset_less=True) + for i in range(8)] + self.b_signed = [Signal(name=f"_b_signed_{i}", reset_less=True) + for i in range(8)] self.pbs = Signal(pbwid, reset_less=True) # outputs - self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)] + self.parts = [Signal(name=f"part_{i}", reset_less=True) + for i in range(n_parts)] - self.not_a_term = Signal(width) - self.neg_lsb_a_term = Signal(width) - self.not_b_term = Signal(width) - self.neg_lsb_b_term = Signal(width) + self.not_a_term = Signal(width, reset_less=True) + self.neg_lsb_a_term = Signal(width, reset_less=True) + self.not_b_term = Signal(width, reset_less=True) + self.neg_lsb_b_term = Signal(width, reset_less=True) def elaborate(self, platform): m = Module() @@ -1060,7 +1059,7 @@ class Mul8_16_32_64(Elaboratable): self.b = Signal(64) # intermediates (needed for unit tests) - self._intermediate_output = Signal(128) + self.intermediate_output = Signal(128) # output self.output = Signal(64) @@ -1147,28 +1146,28 @@ class Mul8_16_32_64(Elaboratable): out_part_pts = add_reduce.o.reg_partition_points m.submodules.add_reduce = add_reduce - m.d.comb += self._intermediate_output.eq(add_reduce.o.output) + m.d.comb += self.intermediate_output.eq(add_reduce.o.output) # create _output_64 m.submodules.io64 = io64 = IntermediateOut(64, 128, 1) - m.d.comb += io64.intermed.eq(self._intermediate_output) + m.d.comb += io64.intermed.eq(self.intermediate_output) for i in range(8): m.d.comb += io64.part_ops[i].eq(out_part_ops[i]) # create _output_32 m.submodules.io32 = io32 = IntermediateOut(32, 128, 2) - m.d.comb += io32.intermed.eq(self._intermediate_output) + m.d.comb += io32.intermed.eq(self.intermediate_output) for i in range(8): m.d.comb += io32.part_ops[i].eq(out_part_ops[i]) # create _output_16 m.submodules.io16 = io16 = IntermediateOut(16, 128, 4) - m.d.comb += io16.intermed.eq(self._intermediate_output) + m.d.comb += io16.intermed.eq(self.intermediate_output) for i in range(8): m.d.comb += io16.part_ops[i].eq(out_part_ops[i]) # create _output_8 m.submodules.io8 = io8 = IntermediateOut(8, 128, 8) - m.d.comb += io8.intermed.eq(self._intermediate_output) + m.d.comb += io8.intermed.eq(self.intermediate_output) for i in range(8): m.d.comb += io8.part_ops[i].eq(out_part_ops[i]) @@ -1203,7 +1202,7 @@ if __name__ == "__main__": m = Mul8_16_32_64() main(m, ports=[m.a, m.b, - m._intermediate_output, + m.intermediate_output, m.output, *m.part_ops, *m.part_pts.values()])