X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Fpart_mul_add%2Fmultiply.py;h=6f770842f8aa048c6afc2b8e54b5013f2e91e985;hb=f20d60b428a9e313866a703f68d5b6e638e296c2;hp=6950a6d9f2779052db7a5b23ab3d98981ad45148;hpb=66657754c88fbd4c684fb9f6eb1fba2c14aeb652;p=ieee754fpu.git diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py index 6950a6d9..6f770842 100644 --- a/src/ieee754/part_mul_add/multiply.py +++ b/src/ieee754/part_mul_add/multiply.py @@ -132,11 +132,11 @@ class FullAdder(Elaboratable): :param width: the bit width of the input and output """ - self.in0 = Signal(width) - self.in1 = Signal(width) - self.in2 = Signal(width) - self.sum = Signal(width) - self.carry = Signal(width) + self.in0 = Signal(width, reset_less=True) + self.in1 = Signal(width, reset_less=True) + self.in2 = Signal(width, reset_less=True) + self.sum = Signal(width, reset_less=True) + self.carry = Signal(width, reset_less=True) def elaborate(self, platform): """Elaborate this module.""" @@ -234,9 +234,9 @@ class PartitionedAdder(Elaboratable): :param partition_points: the input partition points """ self.width = width - self.a = Signal(width) - self.b = Signal(width) - self.output = Signal(width) + self.a = Signal(width, reset_less=True) + self.b = Signal(width, reset_less=True) + self.output = Signal(width, reset_less=True) self.partition_points = PartitionPoints(partition_points) if not self.partition_points.fits_in_width(width): raise ValueError("partition_points doesn't fit in width") @@ -246,17 +246,14 @@ class PartitionedAdder(Elaboratable): expanded_width += 1 expanded_width += 1 self._expanded_width = expanded_width - # XXX these have to remain here due to some horrible nmigen - # simulation bugs involving sync. it is *not* necessary to - # have them here, they should (under normal circumstances) - # be moved into elaborate, as they are entirely local - self._expanded_a = Signal(expanded_width) # includes extra part-points - self._expanded_b = Signal(expanded_width) # likewise. - self._expanded_o = Signal(expanded_width) # likewise. def elaborate(self, platform): """Elaborate this module.""" m = Module() + expanded_a = Signal(self._expanded_width, reset_less=True) + expanded_b = Signal(self._expanded_width, reset_less=True) + expanded_o = Signal(self._expanded_width, reset_less=True) + expanded_index = 0 # store bits in a list, use Cat later. graphviz is much cleaner al, bl, ol, ea, eb, eo = [],[],[],[],[],[] @@ -273,14 +270,14 @@ class PartitionedAdder(Elaboratable): if i in self.partition_points: # add extra bit set to 0 + 0 for enabled partition points # and 1 + 0 for disabled partition points - ea.append(self._expanded_a[expanded_index]) + ea.append(expanded_a[expanded_index]) al.append(~self.partition_points[i]) # add extra bit in a - eb.append(self._expanded_b[expanded_index]) + eb.append(expanded_b[expanded_index]) bl.append(C(0)) # yes, add a zero expanded_index += 1 # skip the extra point. NOT in the output - ea.append(self._expanded_a[expanded_index]) - eb.append(self._expanded_b[expanded_index]) - eo.append(self._expanded_o[expanded_index]) + ea.append(expanded_a[expanded_index]) + eb.append(expanded_b[expanded_index]) + eo.append(expanded_o[expanded_index]) al.append(self.a[i]) bl.append(self.b[i]) ol.append(self.output[i]) @@ -293,8 +290,7 @@ class PartitionedAdder(Elaboratable): # use only one addition to take advantage of look-ahead carry and # special hardware on FPGAs - m.d.comb += self._expanded_o.eq( - self._expanded_a + self._expanded_b) + m.d.comb += expanded_o.eq(expanded_a + expanded_b) return m @@ -302,75 +298,85 @@ FULL_ADDER_INPUT_COUNT = 3 class AddReduceData: - def __init__(self, ppoints, output_width, n_parts): - self.part_ops = [Signal(2, name=f"part_ops_{i}") + def __init__(self, ppoints, n_inputs, output_width, n_parts): + self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True) for i in range(n_parts)] - self.inputs = [Signal(output_width, name=f"inputs[{i}]") - for i in range(len(self.inputs))] - self.reg_partition_points = partition_points.like() + self.inputs = [Signal(output_width, name=f"inputs_{i}", + reset_less=True) + for i in range(n_inputs)] + self.reg_partition_points = ppoints.like() + + def eq_from(self, reg_partition_points, inputs, part_ops): + return [self.reg_partition_points.eq(reg_partition_points)] + \ + [self.inputs[i].eq(inputs[i]) + for i in range(len(self.inputs))] + \ + [self.part_ops[i].eq(part_ops[i]) + for i in range(len(self.part_ops))] def eq(self, rhs): - return [self.reg_partition_points.eq(rhs.reg_partition_points)] + \ - [self.inputs[i].eq(rhs.inputs[i]) - for i in range(len(self.inputs))] + \ - [self.part_ops[i].eq(rhs.part_ops[i]) + return self.eq_from(rhs.reg_partition_points, rhs.inputs, rhs.part_ops) + + +class FinalReduceData: + + def __init__(self, ppoints, output_width, n_parts): + self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True) + for i in range(n_parts)] + self.output = Signal(output_width, reset_less=True) + self.reg_partition_points = ppoints.like() + + def eq_from(self, reg_partition_points, output, part_ops): + return [self.reg_partition_points.eq(reg_partition_points)] + \ + [self.output.eq(output)] + \ + [self.part_ops[i].eq(part_ops[i]) for i in range(len(self.part_ops))] + def eq(self, rhs): + return self.eq_from(rhs.reg_partition_points, rhs.output, rhs.part_ops) + class FinalAdd(Elaboratable): """ Final stage of add reduce """ - def __init__(self, inputs, output_width, register_levels, partition_points, - part_ops): - self.part_ops = part_ops - self.out_part_ops = [Signal(2, name=f"out_part_ops_{i}") - for i in range(len(part_ops))] - self.inputs = list(inputs) - self._resized_inputs = [ - Signal(output_width, name=f"resized_inputs[{i}]") - for i in range(len(self.inputs))] + def __init__(self, n_inputs, output_width, n_parts, register_levels, + partition_points): + self.i = AddReduceData(partition_points, n_inputs, + output_width, n_parts) + self.o = FinalReduceData(partition_points, output_width, n_parts) + self.output_width = output_width + self.n_inputs = n_inputs + self.n_parts = n_parts self.register_levels = list(register_levels) - self.output = Signal(output_width) self.partition_points = PartitionPoints(partition_points) if not self.partition_points.fits_in_width(output_width): raise ValueError("partition_points doesn't fit in output_width") - self._reg_partition_points = self.partition_points.like() def elaborate(self, platform): """Elaborate this module.""" m = Module() - # resize inputs to correct bit-width and optionally add in - # pipeline registers - resized_input_assignments = [self._resized_inputs[i].eq(self.inputs[i]) - for i in range(len(self.inputs))] - copy_part_ops = [self.out_part_ops[i].eq(self.part_ops[i]) - for i in range(len(self.part_ops))] - if 0 in self.register_levels: - m.d.sync += copy_part_ops - m.d.sync += resized_input_assignments - m.d.sync += self._reg_partition_points.eq(self.partition_points) - else: - m.d.comb += copy_part_ops - m.d.comb += resized_input_assignments - m.d.comb += self._reg_partition_points.eq(self.partition_points) - - if len(self.inputs) == 0: + output_width = self.output_width + output = Signal(output_width, reset_less=True) + if self.n_inputs == 0: # use 0 as the default output value - m.d.comb += self.output.eq(0) - elif len(self.inputs) == 1: + m.d.comb += output.eq(0) + elif self.n_inputs == 1: # handle single input - m.d.comb += self.output.eq(self._resized_inputs[0]) + m.d.comb += output.eq(self.i.inputs[0]) else: # base case for adding 2 inputs - assert len(self.inputs) == 2 - adder = PartitionedAdder(len(self.output), - self._reg_partition_points) + assert self.n_inputs == 2 + adder = PartitionedAdder(output_width, self.i.reg_partition_points) m.submodules.final_adder = adder - m.d.comb += adder.a.eq(self._resized_inputs[0]) - m.d.comb += adder.b.eq(self._resized_inputs[1]) - m.d.comb += self.output.eq(adder.output) + m.d.comb += adder.a.eq(self.i.inputs[0]) + m.d.comb += adder.b.eq(self.i.inputs[1]) + m.d.comb += output.eq(adder.output) + + # create output + m.d.comb += self.o.eq_from(self.i.reg_partition_points, output, + self.i.part_ops) + return m @@ -386,8 +392,8 @@ class AddReduceSingle(Elaboratable): supported, except for by ``Signal.eq``. """ - def __init__(self, inputs, output_width, register_levels, partition_points, - part_ops): + def __init__(self, n_inputs, output_width, n_parts, register_levels, + partition_points): """Create an ``AddReduce``. :param inputs: input ``Signal``s to be summed. @@ -396,21 +402,17 @@ class AddReduceSingle(Elaboratable): pipeline registers. :param partition_points: the input partition points. """ + self.n_inputs = n_inputs + self.n_parts = n_parts self.output_width = output_width - self.part_ops = part_ops - self.out_part_ops = [Signal(2, name=f"out_part_ops_{i}") - for i in range(len(part_ops))] - self.inputs = list(inputs) - self._resized_inputs = [ - Signal(output_width, name=f"resized_inputs[{i}]") - for i in range(len(self.inputs))] + self.i = AddReduceData(partition_points, n_inputs, + output_width, n_parts) self.register_levels = list(register_levels) self.partition_points = PartitionPoints(partition_points) if not self.partition_points.fits_in_width(output_width): raise ValueError("partition_points doesn't fit in output_width") - self._reg_partition_points = self.partition_points.like() - max_level = AddReduceSingle.get_max_level(len(self.inputs)) + max_level = AddReduceSingle.get_max_level(n_inputs) for level in self.register_levels: if level > max_level: raise ValueError( @@ -420,11 +422,15 @@ class AddReduceSingle(Elaboratable): # because we need to know what they are (in order to set up the # interconnects back in AddReduce), but cannot do the m.d.comb += # etc because this is not in elaboratable. - self.groups = AddReduceSingle.full_adder_groups(len(self.inputs)) + self.groups = AddReduceSingle.full_adder_groups(n_inputs) self._intermediate_terms = [] + self.adders = [] if len(self.groups) != 0: self.create_next_terms() + self.o = AddReduceData(partition_points, len(self._intermediate_terms), + output_width, n_parts) + @staticmethod def get_max_level(input_count): """Get the maximum level. @@ -452,57 +458,41 @@ class AddReduceSingle(Elaboratable): """Elaborate this module.""" m = Module() - # resize inputs to correct bit-width and optionally add in - # pipeline registers - resized_input_assignments = [self._resized_inputs[i].eq(self.inputs[i]) - for i in range(len(self.inputs))] - copy_part_ops = [self.out_part_ops[i].eq(self.part_ops[i]) - for i in range(len(self.part_ops))] - if 0 in self.register_levels: - m.d.sync += copy_part_ops - m.d.sync += resized_input_assignments - m.d.sync += self._reg_partition_points.eq(self.partition_points) - else: - m.d.comb += copy_part_ops - m.d.comb += resized_input_assignments - m.d.comb += self._reg_partition_points.eq(self.partition_points) + # copy the intermediate terms to the output + for i, value in enumerate(self._intermediate_terms): + m.d.comb += self.o.inputs[i].eq(value) + + # copy reg part points and part ops to output + m.d.comb += self.o.reg_partition_points.eq(self.i.reg_partition_points) + m.d.comb += [self.o.part_ops[i].eq(self.i.part_ops[i]) + for i in range(len(self.i.part_ops))] - for (value, term) in self._intermediate_terms: - m.d.comb += term.eq(value) + # set up the partition mask (for the adders) + part_mask = Signal(self.output_width, reset_less=True) - mask = self._reg_partition_points.as_mask(self.output_width) - m.d.comb += self.part_mask.eq(mask) + mask = self.i.reg_partition_points.as_mask(self.output_width) + m.d.comb += part_mask.eq(mask) # add and link the intermediate term modules for i, (iidx, adder_i) in enumerate(self.adders): setattr(m.submodules, f"adder_{i}", adder_i) - m.d.comb += adder_i.in0.eq(self._resized_inputs[iidx]) - m.d.comb += adder_i.in1.eq(self._resized_inputs[iidx + 1]) - m.d.comb += adder_i.in2.eq(self._resized_inputs[iidx + 2]) - m.d.comb += adder_i.mask.eq(self.part_mask) + m.d.comb += adder_i.in0.eq(self.i.inputs[iidx]) + m.d.comb += adder_i.in1.eq(self.i.inputs[iidx + 1]) + m.d.comb += adder_i.in2.eq(self.i.inputs[iidx + 2]) + m.d.comb += adder_i.mask.eq(part_mask) return m def create_next_terms(self): - # go on to prepare recursive case - intermediate_terms = [] _intermediate_terms = [] def add_intermediate_term(value): - intermediate_term = Signal( - self.output_width, - name=f"intermediate_terms[{len(intermediate_terms)}]") - _intermediate_terms.append((value, intermediate_term)) - intermediate_terms.append(intermediate_term) - - # store mask in intermediary (simplifies graph) - self.part_mask = Signal(self.output_width, reset_less=True) + _intermediate_terms.append(value) # create full adders for this recursive level. # this shrinks N terms to 2 * (N // 3) plus the remainder - self.adders = [] for i in self.groups: adder_i = MaskedFullAdder(self.output_width) self.adders.append((i, adder_i)) @@ -511,18 +501,17 @@ class AddReduceSingle(Elaboratable): add_intermediate_term(adder_i.sum) add_intermediate_term(adder_i.mcarry) # handle the remaining inputs. - if len(self.inputs) % FULL_ADDER_INPUT_COUNT == 1: - add_intermediate_term(self._resized_inputs[-1]) - elif len(self.inputs) % FULL_ADDER_INPUT_COUNT == 2: + if self.n_inputs % FULL_ADDER_INPUT_COUNT == 1: + add_intermediate_term(self.i.inputs[-1]) + elif self.n_inputs % FULL_ADDER_INPUT_COUNT == 2: # Just pass the terms to the next layer, since we wouldn't gain # anything by using a half adder since there would still be 2 terms # and just passing the terms to the next layer saves gates. - add_intermediate_term(self._resized_inputs[-2]) - add_intermediate_term(self._resized_inputs[-1]) + add_intermediate_term(self.i.inputs[-2]) + add_intermediate_term(self.i.inputs[-1]) else: - assert len(self.inputs) % FULL_ADDER_INPUT_COUNT == 0 + assert self.n_inputs % FULL_ADDER_INPUT_COUNT == 0 - self.intermediate_terms = intermediate_terms self._intermediate_terms = _intermediate_terms @@ -550,9 +539,8 @@ class AddReduce(Elaboratable): """ self.inputs = inputs self.part_ops = part_ops - self.out_part_ops = [Signal(2, name=f"out_part_ops_{i}") - for i in range(len(part_ops))] - self.output = Signal(output_width) + n_parts = len(part_ops) + self.o = FinalReduceData(partition_points, output_width, n_parts) self.output_width = output_width self.register_levels = register_levels self.partition_points = partition_points @@ -576,22 +564,25 @@ class AddReduce(Elaboratable): mods = [] next_levels = self.register_levels partition_points = self.partition_points - inputs = self.inputs part_ops = self.part_ops + n_parts = len(part_ops) + inputs = self.inputs + ilen = len(inputs) while True: - next_level = AddReduceSingle(inputs, self.output_width, next_levels, - partition_points, part_ops) - mods.append(next_level) - next_levels = list(AddReduce.next_register_levels(next_levels)) - partition_points = next_level._reg_partition_points - inputs = next_level.intermediate_terms - part_ops = next_level.out_part_ops groups = AddReduceSingle.full_adder_groups(len(inputs)) if len(groups) == 0: break + next_level = AddReduceSingle(ilen, self.output_width, n_parts, + next_levels, partition_points) + mods.append(next_level) + next_levels = list(AddReduce.next_register_levels(next_levels)) + partition_points = next_level.i.reg_partition_points + inputs = next_level.o.inputs + ilen = len(inputs) + part_ops = next_level.i.part_ops - next_level = FinalAdd(inputs, self.output_width, next_levels, - partition_points, part_ops) + next_level = FinalAdd(ilen, self.output_width, n_parts, + next_levels, partition_points) mods.append(next_level) self.levels = mods @@ -603,11 +594,24 @@ class AddReduce(Elaboratable): for i, next_level in enumerate(self.levels): setattr(m.submodules, "next_level%d" % i, next_level) + partition_points = self.partition_points + inputs = self.inputs + part_ops = self.part_ops + n_parts = len(part_ops) + n_inputs = len(inputs) + output_width = self.output_width + i = AddReduceData(partition_points, n_inputs, output_width, n_parts) + m.d.comb += i.eq_from(partition_points, inputs, part_ops) + for idx in range(len(self.levels)): + mcur = self.levels[idx] + if 0 in mcur.register_levels: + m.d.sync += mcur.i.eq(i) + else: + m.d.comb += mcur.i.eq(i) + i = mcur.o # for next loop + # output comes from last module - m.d.comb += self.output.eq(next_level.output) - copy_part_ops = [self.out_part_ops[i].eq(next_level.out_part_ops[i]) - for i in range(len(self.part_ops))] - m.d.comb += copy_part_ops + m.d.comb += self.o.eq(i) return m @@ -775,7 +779,8 @@ class Parts(Elaboratable): # inputs self.epps = PartitionPoints.like(epps, name="epps") # expanded points # outputs - self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)] + self.parts = [Signal(name=f"part_{i}", reset_less=True) + for i in range(n_parts)] def elaborate(self, platform): m = Module() @@ -828,19 +833,22 @@ class Part(Elaboratable): self.epps = epps # inputs - self.a = Signal(64) - self.b = Signal(64) - self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)] - self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)] + self.a = Signal(64, reset_less=True) + self.b = Signal(64, reset_less=True) + self.a_signed = [Signal(name=f"a_signed_{i}", reset_less=True) + for i in range(8)] + self.b_signed = [Signal(name=f"_b_signed_{i}", reset_less=True) + for i in range(8)] self.pbs = Signal(pbwid, reset_less=True) # outputs - self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)] + self.parts = [Signal(name=f"part_{i}", reset_less=True) + for i in range(n_parts)] - self.not_a_term = Signal(width) - self.neg_lsb_a_term = Signal(width) - self.not_b_term = Signal(width) - self.neg_lsb_b_term = Signal(width) + self.not_a_term = Signal(width, reset_less=True) + self.neg_lsb_a_term = Signal(width, reset_less=True) + self.not_b_term = Signal(width, reset_less=True) + self.neg_lsb_b_term = Signal(width, reset_less=True) def elaborate(self, platform): m = Module() @@ -1051,7 +1059,7 @@ class Mul8_16_32_64(Elaboratable): self.b = Signal(64) # intermediates (needed for unit tests) - self._intermediate_output = Signal(128) + self.intermediate_output = Signal(128) # output self.output = Signal(64) @@ -1134,32 +1142,32 @@ class Mul8_16_32_64(Elaboratable): expanded_part_pts, self.part_ops) - out_part_ops = add_reduce.levels[-1].out_part_ops - out_part_pts = add_reduce.levels[-1]._reg_partition_points + out_part_ops = add_reduce.o.part_ops + out_part_pts = add_reduce.o.reg_partition_points m.submodules.add_reduce = add_reduce - m.d.comb += self._intermediate_output.eq(add_reduce.output) + m.d.comb += self.intermediate_output.eq(add_reduce.o.output) # create _output_64 m.submodules.io64 = io64 = IntermediateOut(64, 128, 1) - m.d.comb += io64.intermed.eq(self._intermediate_output) + m.d.comb += io64.intermed.eq(self.intermediate_output) for i in range(8): m.d.comb += io64.part_ops[i].eq(out_part_ops[i]) # create _output_32 m.submodules.io32 = io32 = IntermediateOut(32, 128, 2) - m.d.comb += io32.intermed.eq(self._intermediate_output) + m.d.comb += io32.intermed.eq(self.intermediate_output) for i in range(8): m.d.comb += io32.part_ops[i].eq(out_part_ops[i]) # create _output_16 m.submodules.io16 = io16 = IntermediateOut(16, 128, 4) - m.d.comb += io16.intermed.eq(self._intermediate_output) + m.d.comb += io16.intermed.eq(self.intermediate_output) for i in range(8): m.d.comb += io16.part_ops[i].eq(out_part_ops[i]) # create _output_8 m.submodules.io8 = io8 = IntermediateOut(8, 128, 8) - m.d.comb += io8.intermed.eq(self._intermediate_output) + m.d.comb += io8.intermed.eq(self.intermediate_output) for i in range(8): m.d.comb += io8.part_ops[i].eq(out_part_ops[i]) @@ -1194,7 +1202,7 @@ if __name__ == "__main__": m = Mul8_16_32_64() main(m, ports=[m.a, m.b, - m._intermediate_output, + m.intermediate_output, m.output, *m.part_ops, *m.part_pts.values()])