X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Fpart_mul_add%2Fmultiply.py;h=92afc2bbd85f18e6305a7f85576af793d2d8e2af;hb=7b4588e1710b0e997b9dd5d1f0376150afe276ce;hp=672bbfd33acdef4510167e6ec1d8c78e0bf3603f;hpb=5e1e5b602e087661f3ee58d608ae1396ecbc14b3;p=ieee754fpu.git

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index 672bbfd3..92afc2bb 100644
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -616,7 +616,7 @@ class AddReduce(Elaboratable):
         m.d.comb += i.eq_from(partition_points, inputs, part_ops)
         for idx in range(len(self.levels)):
             mcur = self.levels[idx]
-            if 0 in mcur.register_levels:
+            if idx in self.register_levels:
                 m.d.sync += mcur.i.eq(i)
             else:
                 m.d.comb += mcur.i.eq(i)