X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Flib%2FMemoryMap.bsv;h=a46ef3ac738448ea007a46be1503c916fb8d1364;hb=c13d0c375a0930795f722edaaea7495b679da1b0;hp=16d97695c89682aa9736637a9a77046a19db962c;hpb=7fcae1912869a2b23b72365ac972a0abea906899;p=shakti-core.git

diff --git a/src/lib/MemoryMap.bsv b/src/lib/MemoryMap.bsv
index 16d9769..a46ef3a 100644
--- a/src/lib/MemoryMap.bsv
+++ b/src/lib/MemoryMap.bsv
@@ -41,11 +41,11 @@ package MemoryMap;
 function Tuple2 #(Bool, Bit#(TLog#(Num_Fast_Slaves)))
                     fn_addr_to_slave_num  (Bit#(`PADDR) addr);
 
-    let ft = FastTuple2(addr);
+    let ft = fn_addr_to_fastslave_num(addr);
     Bool isfast = tpl_1(ft);
     Bit#(TLog#(Num_Fast_Slaves)) x = tpl_2(ft);
 
-    let st = SlowTuple2(addr);
+    let st = fn_slow_address_mapping(addr);
     Bool isslow = tpl_1(st);
     Bit#(TLog#(Num_Slow_Slaves)) y = tpl_2(st);
     if (isfast)
@@ -60,11 +60,16 @@ endfunction
 function Bool is_IO_Addr(Bit#(`PADDR) addr); // TODO Shuold be PADDR
         if(addr>=`DebugBase && addr<=`DebugEnd)
             return (True);
-        else if(addr>=`SDRAMMemBase && addr<=`SDRAMMemEnd)
-        `ifdef FlexBus
-                return (True);
-        `else
-            return (False);
+        else
+        `ifdef SDR0_0_Base
+            if(addr>=`SDR0_0_Base && addr<=`SDR0_0_End)
+            `ifdef FlexBus
+                    return (True);
+            `else
+                return (False);
+            `endif
+         `else
+             return (False);
         `endif
         `ifdef BOOTROM
             else if(addr>=`BootRomBase && addr<=`BootRomEnd)