X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Flib%2FMemoryMap.bsv;h=a46ef3ac738448ea007a46be1503c916fb8d1364;hb=c13d0c375a0930795f722edaaea7495b679da1b0;hp=f664200114186d3b093893acfcf589470b703790;hpb=e550d93bbebb250b623095da6b4ce4b81aa284d2;p=shakti-core.git diff --git a/src/lib/MemoryMap.bsv b/src/lib/MemoryMap.bsv index f664200..a46ef3a 100644 --- a/src/lib/MemoryMap.bsv +++ b/src/lib/MemoryMap.bsv @@ -31,51 +31,56 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. package MemoryMap; /*=== Project imports ==== */ import defined_types::*; - import SoC::*; - import slow_peripherals::*; + import fast_memory_map::*; + import slow_memory_map::*; `include "instance_defines.bsv" - `include "core_defines.bsv" + `include "core_parameters.bsv" /*========================= */ -function Tuple2 #(Bool, Bit#(TLog#(Num_Slaves))) +function Tuple2 #(Bool, Bit#(TLog#(Num_Fast_Slaves))) fn_addr_to_slave_num (Bit#(`PADDR) addr); - Bool isfast; - Bit#(TLog#(Num_Slaves) y; - FastTuple2(isfast, y); - if (isfast) - return tuple2(isfast, y); + let ft = fn_addr_to_fastslave_num(addr); + Bool isfast = tpl_1(ft); + Bit#(TLog#(Num_Fast_Slaves)) x = tpl_2(ft); - Bool isslow; - Bit#(TLog#(Num_Slow_Slaves) y; - SlowTuple2(isslow, y); - if (isslow) + let st = fn_slow_address_mapping(addr); + Bool isslow = tpl_1(st); + Bit#(TLog#(Num_Slow_Slaves)) y = tpl_2(st); + if (isfast) + return tuple2(isfast, x); + else if (isslow) return tuple2(True,fromInteger(valueOf(SlowPeripheral_slave_num))); - - return tuple2(False,?); + else + return tuple2(False,?); endfunction function Bool is_IO_Addr(Bit#(`PADDR) addr); // TODO Shuold be PADDR - if(addr>=`DebugBase && addr<=`DebugEnd) - return (True); - else if(addr>=`SDRAMMemBase && addr<=`SDRAMMemEnd) - `ifdef FlexBus - return (True); - `else - return (False); - `endif - `ifdef BOOTROM - else if(addr>=`BootRomBase && addr<=`BootRomEnd) - return (False); - `endif - `ifdef TCMemory - else if(addr>=`TCMBase && addr<=`TCMEnd) - return (False); - `endif - else - return True; + if(addr>=`DebugBase && addr<=`DebugEnd) + return (True); + else + `ifdef SDR0_0_Base + if(addr>=`SDR0_0_Base && addr<=`SDR0_0_End) + `ifdef FlexBus + return (True); + `else + return (False); + `endif + `else + return (False); + `endif + `ifdef BOOTROM + else if(addr>=`BootRomBase && addr<=`BootRomEnd) + return (False); + `endif + `ifdef TCMemory + else if(addr>=`TCMBase && addr<=`TCMEnd) + return (False); + `endif + else + return True; endfunction endpackage