X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIO.scala;h=ae468cec2f909bb8511ea786092ef9ce7c484c7b;hb=fb9dd313741196a062e6a0f6462cf3a2bce710a9;hp=12ac055bbb1d74ed224483129d39ba20e7ed2969;hpb=66b2fd11bd1ec6a8a05c4929893c51c7570284fd;p=sifive-blocks.git

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index 12ac055..ae468ce 100644
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -2,10 +2,10 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
-import config.Parameters
-import regmapper._
-import uncore.tilelink2._
-import util.{AsyncResetRegVec, GenericParameterizedBundle}
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
 
 case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)