X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIOPeriphery.scala;h=20f8b5d8172438746251a471dd1f205d346ef78a;hb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;hp=f2fe5869201ce660e00bde8bf187cb5aadd5996c;hpb=03be9aba67b185b5454e9013901e6f873f62ac9d;p=sifive-blocks.git

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index f2fe586..20f8b5d 100644
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -2,27 +2,31 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
+import config.Field
 import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
+import rocketchip.{
+  HasTopLevelNetworks,
+  HasTopLevelNetworksBundle,
+  HasTopLevelNetworksModule
+}
 import uncore.tilelink2.TLFragmenter
 
-trait PeripheryGPIO {
-  this: TopNetwork { val gpioConfig: GPIOConfig } =>
-  val gpio = LazyModule(new TLGPIO(gpioConfig))
-  gpio.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+case object PeripheryGPIOKey extends Field[GPIOParams]
+
+trait HasPeripheryGPIO extends HasTopLevelNetworks {
+  val gpioParams = p(PeripheryGPIOKey)
+  val gpio = LazyModule(new TLGPIO(peripheryBusBytes, gpioParams))
+  gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
   intBus.intnode := gpio.intnode
 }
 
-trait PeripheryGPIOBundle {
-  this: { val gpioConfig: GPIOConfig } =>
-  val gpio = new GPIOPortIO(gpioConfig)
+trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
+  val outer: HasPeripheryGPIO
+  val gpio = new GPIOPortIO(outer.gpioParams)
 }
 
-trait PeripheryGPIOModule {
-  this: TopNetworkModule {
-    val gpioConfig: GPIOConfig
-    val outer: PeripheryGPIO
-    val io: PeripheryGPIOBundle
-  } =>
+trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
+  val outer: HasPeripheryGPIO
+  val io: HasPeripheryGPIOBundle
   io.gpio <> outer.gpio.module.io.port
 }