X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIOPeriphery.scala;h=d3b9cf5f17a49ba0c67aa54cdf27832f2267d158;hb=0a80d1987d35046858c36a4fa462410b54a126f0;hp=cd658f17dd30625004f39fbfd49113d0e562c483;hpb=2bad829e6e722412dc6de726f1617dafdb658a1b;p=sifive-blocks.git

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index cd658f1..d3b9cf5 100644
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -3,19 +3,18 @@ package sifive.blocks.devices.gpio
 
 import Chisel._
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.TLFragmenter
 import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
-trait HasPeripheryGPIO extends HasSystemNetworks {
+trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
   val gpioParams = p(PeripheryGPIOKey)
-  val gpios = gpioParams map {params =>
-    val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
-    gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := gpio.intnode
+  val gpios = gpioParams map { params =>
+    val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
+    gpio.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := gpio.intnode
     gpio
   }
 }