X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2C.scala;h=0c487642ab5f1fcb473e38bd51a8ebbbebcf3148;hb=095cb158dd0e7fe87b3cf5afa30b6db3ec4dc266;hp=da555496a8297f1a1d69a9d7cbeb90a67b5b3b20;hpb=72e4b60d81e5ae1cbc518c9a3bda486a56dfca8c;p=sifive-blocks.git

diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala
index da55549..0c48764 100644
--- a/src/main/scala/devices/i2c/I2C.scala
+++ b/src/main/scala/devices/i2c/I2C.scala
@@ -182,10 +182,10 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap {
   }
 
   val sclOen     = Reg(init = true.B)
-  io.port.scl.oe := sclOen
+  io.port.scl.oe := !sclOen
 
   val sdaOen     = Reg(init = true.B)
-  io.port.sda.oe := sdaOen
+  io.port.sda.oe := !sdaOen
 
   val sdaChk     = Reg(init = false.B)       // check SDA output (Multi-master arbitration)