X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2C.scala;h=aecf2dca476cde9bb5bfb94adbb650ed988b0959;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hp=0fcf64080e28ad44dfeeb3b20488731783060096;hpb=d474b5ceb25e76501fb8a9bb77f541e563f589be;p=sifive-blocks.git diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala index 0fcf640..aecf2dc 100644 --- a/src/main/scala/devices/i2c/I2C.scala +++ b/src/main/scala/devices/i2c/I2C.scala @@ -1,22 +1,54 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE revB.2 compliant I2C Master controller Top-level //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// This code was re-written in Chisel by SiFive, Inc. // See LICENSE for license details. +// WISHBONE interface replaced by Tilelink2 + package sifive.blocks.devices.i2c import Chisel._ -import config._ -import util._ -import regmapper._ -import uncore.tilelink2._ -import rocketchip.PeripheryBusConfig -import util.AsyncResetRegVec -import sifive.blocks.devices.gpio.{GPIOPinCtrl} - -case class I2CConfig(address: BigInt) - -trait HasI2CParameters { - implicit val p: Parameters - val params: I2CConfig - val c = params -} +import chisel3.experimental.MultiIOModule +import freechips.rocketchip.config._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.{AsyncResetRegVec, Majority} + +case class I2CParams(address: BigInt) class I2CPin extends Bundle { val in = Bool(INPUT) @@ -29,12 +61,13 @@ class I2CPort extends Bundle { val sda = new I2CPin } -trait I2CBundle extends Bundle with HasI2CParameters { +trait HasI2CBundleContents extends Bundle { val port = new I2CPort } -trait I2CModule extends Module with HasI2CParameters with HasRegMap { - val io: I2CBundle +trait HasI2CModuleContents extends MultiIOModule with HasRegMap { + val io: HasI2CBundleContents + val params: I2CParams val I2C_CMD_NOP = UInt(0x00) val I2C_CMD_START = UInt(0x01) @@ -103,8 +136,8 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap { fSDA := Cat(fSDA, io.port.sda.in) } - val sSCL = Reg(init = true.B, next = (new Majority(fSCL.toBools.toSet)).out) - val sSDA = Reg(init = true.B, next = (new Majority(fSDA.toBools.toSet)).out) + val sSCL = Reg(init = true.B, next = Majority(fSCL)) + val sSDA = Reg(init = true.B, next = Majority(fSDA)) val dSCL = Reg(init = true.B, next = sSCL) val dSDA = Reg(init = true.B, next = sSDA) @@ -142,10 +175,10 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap { } val sclOen = Reg(init = true.B) - io.port.scl.oe := sclOen + io.port.scl.oe := !sclOen val sdaOen = Reg(init = true.B) - io.port.sda.oe := sdaOen + io.port.sda.oe := !sdaOen val sdaChk = Reg(init = false.B) // check SDA output (Multi-master arbitration) @@ -484,12 +517,28 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap { status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck + val statusReadReady = Reg(init = true.B) + when (!statusReadReady) { + statusReadReady := true.B + } + + // statusReadReady, regmap( I2CCtrlRegs.prescaler_lo -> Seq(RegField(8, prescaler.lo)), I2CCtrlRegs.prescaler_hi -> Seq(RegField(8, prescaler.hi)), I2CCtrlRegs.control -> control.elements.map{ case(name, e) => RegField(e.getWidth, e.asInstanceOf[UInt]) }.toSeq, I2CCtrlRegs.data -> Seq(RegField(8, r = RegReadFn(receivedData), w = RegWriteFn(transmitData))), - I2CCtrlRegs.cmd_status -> Seq(RegField(8, r = RegReadFn(status.asUInt), w = RegWriteFn(nextCmd))) + I2CCtrlRegs.cmd_status -> Seq(RegField(8, r = RegReadFn{ ready => + (statusReadReady, status.asUInt) + }, + w = RegWriteFn((valid, data) => { + when (valid) { + statusReadReady := false.B + nextCmd := data + } + true.B + } + ))) ) // tie off unused bits @@ -500,16 +549,8 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap { interrupts(0) := status.irqFlag & control.intEn } -// Copied from UART.scala -class Majority(in: Set[Bool]) { - private val n = (in.size >> 1) + 1 - private val clauses = in.subsets(n).map(_.reduce(_ && _)) - val out = clauses.reduce(_ || _) -} - - // Magic TL2 Incantation to create a TL2 Slave -class TLI2C(c: I2CConfig)(implicit p: Parameters) - extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)( - new TLRegBundle(c, _) with I2CBundle)( - new TLRegModule(c, _, _) with I2CModule) +class TLI2C(w: Int, c: I2CParams)(implicit p: Parameters) + extends TLRegisterRouter(c.address, "i2c", Seq("sifive,i2c0"), interrupts = 1, beatBytes = w)( + new TLRegBundle(c, _) with HasI2CBundleContents)( + new TLRegModule(c, _, _) with HasI2CModuleContents)