X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPeriphery.scala;h=775eb80380b66644ea09f39e8bee55342db7dd83;hb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;hp=09bb9cc90cbe825ad1f75491f9ca74fe8cc049e5;hpb=03be9aba67b185b5454e9013901e6f873f62ac9d;p=sifive-blocks.git

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 09bb9cc..775eb80 100644
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -2,31 +2,31 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
+import config.Field
 import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
+import rocketchip.{HasTopLevelNetworks,HasTopLevelNetworksBundle,HasTopLevelNetworksModule}
 import uncore.tilelink2.TLFragmenter
 
-trait PeripheryI2C {
-  this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
-  val i2c = i2cConfigs.zipWithIndex.map { case (c, i) =>
-    val i2c = LazyModule(new TLI2C(c))
-    i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+case object PeripheryI2CKey extends Field[Seq[I2CParams]]
+
+trait HasPeripheryI2C extends HasTopLevelNetworks {
+  val i2cParams = p(PeripheryI2CKey)
+  val i2c = i2cParams map { params =>
+    val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
+    i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := i2c.intnode
     i2c
   }
 }
 
-trait PeripheryI2CBundle {
-  this: { val i2cConfigs: Seq[I2CConfig] } =>
-  val i2cs = Vec(i2cConfigs.size, new I2CPort)
+trait HasPeripheryI2CBundle extends HasTopLevelNetworksBundle{
+  val outer: HasPeripheryI2C
+  val i2cs = Vec(outer.i2cParams.size, new I2CPort)
 }
 
-trait PeripheryI2CModule {
-  this: TopNetworkModule {
-    val i2cConfigs: Seq[I2CConfig]
-    val outer: PeripheryI2C
-    val io: PeripheryI2CBundle
-  } =>
+trait HasPeripheryI2CModule extends HasTopLevelNetworksModule {
+  val outer: HasPeripheryI2C
+  val io: HasPeripheryI2CBundle
   (io.i2cs zip outer.i2c).foreach { case (io, device) =>
     io <> device.module.io.port
   }