X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPeriphery.scala;h=7ee50158e344cd58c25a8e0151c1aded3464bde9;hb=d474b5ceb25e76501fb8a9bb77f541e563f589be;hp=8eb741873cc6c920069a2a4fb033fc91048d6e31;hpb=3781d1fb1aa2c878ea7931a7bcf346c0ea95a619;p=sifive-blocks.git

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 8eb7418..7ee5015 100644
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -10,7 +10,6 @@ trait PeripheryI2C {
   this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
   val i2cDevices = i2cConfigs.zipWithIndex.map { case (c, i) =>
     val i2c = LazyModule(new TLI2C(c))
-    i2c.suggestName(s"i2c$i")
     i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := i2c.intnode
     i2c