X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPeriphery.scala;h=c9de71b1755cd2557cb5b77419daccbe7b2c9538;hb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;hp=d9c3ff4085d3aa515f1dcc309dd6eed5d77d8002;hpb=b06b80dccdf4e71b37866cc0e32a800a2b1a62d1;p=sifive-blocks.git

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index d9c3ff4..c9de71b 100644
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -2,10 +2,10 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.{HasSystemNetworks}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.{HasSystemNetworks}
+import freechips.rocketchip.tilelink.TLFragmenter
 
 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
 
@@ -20,13 +20,7 @@ trait HasPeripheryI2C extends HasSystemNetworks {
 }
 
 trait HasPeripheryI2CBundle {
-  val i2cs: Vec[I2CPort]
-
-  def toGPIOPins(syncStages: Int = 0): Seq[I2CGPIOPort] = i2cs.map { i =>
-    val pin = Module(new I2CGPIOPort(syncStages))
-    pin.io.i2c <> i
-    pin
-  }
+  val i2c: Vec[I2CPort]
 }
 
 trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {