X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPins.scala;h=6bf40aedd5526975ebfd5fe7ecb186b643927c09;hb=97c3fcb4b67092604bf96cef551c56ccf7d36822;hp=df6dd6f3bd13d33da2e4025e5135f39008f0d877;hpb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;p=sifive-blocks.git

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index df6dd6f..6bf40ae 100644
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -3,24 +3,28 @@ package sifive.blocks.devices.i2c
 
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
-
 
 class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
 
   val scl: T = pingen()
   val sda: T = pingen()
 
-  def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
+
+  def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
     withClockAndReset(clock, reset) {
       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
       scl.o.oe := i2c.scl.oe
-      i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true))
+      i2c.scl.in := SyncResetSynchronizerShiftReg(scl.i.ival, syncStages, init = Bool(true),
+        name = Some("i2c_scl_sync"))
 
       sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
       sda.o.oe := i2c.sda.oe
-      i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true))
+      i2c.sda.in := SyncResetSynchronizerShiftReg(sda.i.ival, syncStages, init = Bool(true),
+        name = Some("i2c_sda_sync"))
     }
   }
 }