X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fmockaon%2FMockAONPeriphery.scala;h=240f89bef173dab65b3d053c9eeab8c0f9633052;hb=fb9dd313741196a062e6a0f6462cf3a2bce710a9;hp=91fa4fb93273e509c194f77e84142bcdb3f4f528;hpb=66b2fd11bd1ec6a8a05c4929893c51c7570284fd;p=sifive-blocks.git

diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
index 91fa4fb..240f89b 100644
--- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala
+++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
@@ -2,11 +2,11 @@
 package sifive.blocks.devices.mockaon
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import rocketchip.{HasSystemNetworks, HasCoreplexRISCVPlatform}
-import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
-import util.ResetCatchAndSync
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.{HasSystemNetworks, HasCoreplexRISCVPlatform}
+import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource, TLFragmenter}
+import freechips.rocketchip.util.ResetCatchAndSync
 
 case object PeripheryMockAONKey extends Field[MockAONParams]