X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPeriphery.scala;h=63bbfabccc48a6f7e0a9dd256193a0fe378a93fe;hb=4d74e8f67f871df93f7bb2dfb2fa8bffb641fc4a;hp=d22de54db38ef82091e55e0600ba34e696c858c3;hpb=dacca7e7b127f5578373c8aa28195ae189d81e51;p=sifive-blocks.git

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index d22de54..63bbfab 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -2,30 +2,27 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.TLFragmenter
-import util.HeterogeneousBag
-
-import sifive.blocks.devices.gpio._
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.util.HeterogeneousBag
+import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 
 class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
-class PWMPinsIO(val c: PWMParams) extends Bundle {
-  val pwm = Vec(c.ncmp, new GPIOPin)
-}
+class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
 
-class PWMGPIOPort(val c: PWMParams) extends Module {
-  val io = new Bundle {
-    val pwm = new PWMPortIO(c).flip()
-    val pins = new PWMPinsIO(c)
-  }
+  val pwm: Vec[T] = Vec(c.ncmp, pingen())
 
-  GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
+  def fromPWMPort(port: PWMPortIO) {
+    (pwm zip port.port)  foreach {case (pin, port) =>
+      pin.outputPin(port)
+    }
+  }
 }
 
 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
@@ -43,11 +40,6 @@ trait HasPeripheryPWM extends HasSystemNetworks {
 trait HasPeripheryPWMBundle {
   val pwms: HeterogeneousBag[PWMPortIO]
 
-  def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
-    val pins = Module(new PWMGPIOPort(p.c))
-    pins.io.pwm <> p
-    pins.io.pins
-  }
 }
 
 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {