X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPeriphery.scala;h=7b5989661e1b472203a904a7f4499a40118319ba;hb=d4bb8a77ea7a0a9545dcaf93a4a2a32671c2dd47;hp=7e616da39ffc0fff226923f1b72d04eb22bde383;hpb=79f64de12cac914c0c195dc876f34adcaf15f7d5;p=sifive-blocks.git

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 7e616da..7b59896 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -3,27 +3,23 @@ package sifive.blocks.devices.pwm
 
 import Chisel._
 import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksBundle,
-  HasTopLevelNetworksModule
-}
+import diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import rocketchip.HasSystemNetworks
 import uncore.tilelink2.TLFragmenter
 import util.HeterogeneousBag
 
 import sifive.blocks.devices.gpio._
 
-class PWMPortIO(c: PWMParams) extends Bundle {
+class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
-class PWMPinsIO(c: PWMParams) extends Bundle {
+class PWMPinsIO(val c: PWMParams) extends Bundle {
   val pwm = Vec(c.ncmp, new GPIOPin)
 }
 
-class PWMGPIOPort(c: PWMParams) extends Module {
+class PWMGPIOPort(val c: PWMParams) extends Module {
   val io = new Bundle {
     val pwm = new PWMPortIO(c).flip()
     val pins = new PWMPinsIO(c)
@@ -34,7 +30,7 @@ class PWMGPIOPort(c: PWMParams) extends Module {
 
 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
-trait HasPeripheryPWM extends HasTopLevelNetworks {
+trait HasPeripheryPWM extends HasSystemNetworks {
   val pwmParams = p(PeripheryPWMKey)
   val pwms = pwmParams map { params =>
     val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
@@ -44,16 +40,21 @@ trait HasPeripheryPWM extends HasTopLevelNetworks {
   }
 }
 
-trait HasPeripheryPWMBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripheryPWM
-  val pwms = HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))
+trait HasPeripheryPWMBundle {
+  val pwms: HeterogeneousBag[PWMPortIO]
+
+  def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMGPIOPort] = pwms.map { p =>
+    val pin = Module(new PWMGPIOPort(p.c))
+    pin.io.pwm <> p
+    pin
+  }
 }
 
-trait HasPeripheryPWMModule extends HasTopLevelNetworksModule {
+trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
   val outer: HasPeripheryPWM
-  val io: HasPeripheryPWMBundle
+  val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
 
-  (io.pwms zip outer.pwms) foreach { case (io, device) =>
+  (pwms zip outer.pwms) foreach { case (io, device) =>
     io.port := device.module.io.gpio
   }
 }