X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPeriphery.scala;h=ff5b6bbe1a20aff22e859e3a27c5b65f1ad0a430;hb=0a80d1987d35046858c36a4fa462410b54a126f0;hp=f83cbafdfe9780ea83e865a8d94b65c4de9a8c4a;hpb=2bad829e6e722412dc6de726f1617dafdb658a1b;p=sifive-blocks.git

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index f83cbaf..ff5b6bb 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -3,11 +3,10 @@ package sifive.blocks.devices.pwm
 
 import Chisel._
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import freechips.rocketchip.util.HeterogeneousBag
-import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
+import sifive.blocks.devices.pinctrl.{Pin}
 
 class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
@@ -30,12 +29,12 @@ class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
 
 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
-trait HasPeripheryPWM extends HasSystemNetworks {
+trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
   val pwmParams = p(PeripheryPWMKey)
   val pwms = pwmParams map { params =>
-    val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
-    pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := pwm.intnode
+    val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
+    pwm.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := pwm.intnode
     pwm
   }
 }