X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIArbiter.scala;h=56c484ed593b46e8321deec29c621418065026a7;hb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;hp=b47cea3a4ba39e673056fa623617a054c12aa4a8;hpb=03be9aba67b185b5454e9013901e6f873f62ac9d;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIArbiter.scala b/src/main/scala/devices/spi/SPIArbiter.scala
index b47cea3..56c484e 100644
--- a/src/main/scala/devices/spi/SPIArbiter.scala
+++ b/src/main/scala/devices/spi/SPIArbiter.scala
@@ -3,11 +3,11 @@ package sifive.blocks.devices.spi
 
 import Chisel._
 
-class SPIInnerIO(c: SPIConfigBase) extends SPILinkIO(c) {
+class SPIInnerIO(c: SPIParamsBase) extends SPILinkIO(c) {
   val lock = Bool(OUTPUT)
 }
 
-class SPIArbiter(c: SPIConfigBase, n: Int) extends Module {
+class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
   val io = new Bundle {
     val inner = Vec(n, new SPIInnerIO(c)).flip
     val outer = new SPILinkIO(c)