X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIMedia.scala;h=584b8d9f0e3462e9cbf14aba40bb99407c013cfc;hb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;hp=1f049e35fcf152cab312bb125a905708103c19e8;hpb=03be9aba67b185b5454e9013901e6f873f62ac9d;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIMedia.scala b/src/main/scala/devices/spi/SPIMedia.scala
index 1f049e3..584b8d9 100644
--- a/src/main/scala/devices/spi/SPIMedia.scala
+++ b/src/main/scala/devices/spi/SPIMedia.scala
@@ -3,7 +3,7 @@ package sifive.blocks.devices.spi
 
 import Chisel._
 
-class SPILinkIO(c: SPIConfigBase) extends SPIBundle(c) {
+class SPILinkIO(c: SPIParamsBase) extends SPIBundle(c) {
   val tx = Decoupled(Bits(width = c.frameBits))
   val rx = Valid(Bits(width = c.frameBits)).flip
 
@@ -17,7 +17,7 @@ class SPILinkIO(c: SPIConfigBase) extends SPIBundle(c) {
   val active = Bool(INPUT)
 }
 
-class SPIMedia(c: SPIConfigBase) extends Module {
+class SPIMedia(c: SPIParamsBase) extends Module {
   val io = new Bundle {
     val port = new SPIPortIO(c)
     val ctrl = new Bundle {