X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=37fe3d9081beff59aa9106bc287b09c6acc952c9;hb=00fbfb6dd8bd8d52588fc58ab98165ffdc132d17;hp=dd76d15db4df1ca8149bef39a53c55f0b8cb2478;hpb=3dee15277598e45d7ac9d435f0365989c6d00f7e;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index dd76d15..37fe3d9 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -3,18 +3,19 @@ package sifive.blocks.devices.spi
 
 import Chisel._
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.subsystem.BaseSubsystem
 import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
 import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
 import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripherySPIKey extends Field[Seq[SPIParams]]
 
-trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
+trait HasPeripherySPI { this: BaseSubsystem =>
   val spiParams = p(PeripherySPIKey)  
-  val spis = spiParams map { params =>
-    val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
-    spi.rnode := pbus.toVariableWidthSlaves
+  val spis = spiParams.zipWithIndex.map { case(params, i) =>
+    val name = Some(s"spi_$i")
+    val spi = LazyModule(new TLSPI(pbus.beatBytes, params)).suggestName(name)
+    pbus.toVariableWidthSlave(name) { spi.rnode }
     ibus.fromSync := spi.intnode
     spi
   }
@@ -36,15 +37,16 @@ trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle
 
 case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
-trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
+trait HasPeripherySPIFlash { this: BaseSubsystem =>
   val spiFlashParams = p(PeripherySPIFlashKey)  
-  val qspis = spiFlashParams map { params =>
+  val qspis = spiFlashParams.zipWithIndex.map { case(params, i) =>
+    val name = Some(s"qspi_$i")
     val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
-    qspi.rnode := pbus.toVariableWidthSlaves
-    (qspi.fnode
-      := TLFragmenter(1, pbus.blockBytes)
-      := TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
-      := pbus.toFixedWidthSlaves)
+    pbus.toVariableWidthSlave(name) { qspi.rnode }
+    qspi.fnode := pbus.toFixedWidthSlave(name) {
+      TLFragmenter(1, pbus.blockBytes) :=
+        TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
+    }
     ibus.fromSync := qspi.intnode
     qspi
   }